Low voltage second-order alpha function synapse

This paper introduces a Transimpedance Amplifier (TIA) design capable of producing an incremental input resistance in the ohmic range, for input signals in the microampere range, such as are encountered in the design of instrumentation for electrochemical ampero-metric sensors, optical-sensing and current-mode circuits. This low input-resistance is achieved using an input stage incorporating negative feedback. In a Cadence simulation of an exemplary design using a 180 nm CMOS process and operating with?±?1.8 V supply rails, the input resistance is 1.05 ohms and the power dissipation is 93.6 µW. The bandwidth, for a gain of 100 dBohm, exceeded 9 MHz. For a 1µA, 1 MHz sinusoidal input signal the Total Harmonic Distortion, with this gain, is less than 1%. The input referred noise current with zero photodiode capacitance is 2.09 pA/√Hz and with a photodiode capacitance of 2pF is 8.52 pA/√Hz. Graphical data is presented to show the effect of a photodiode capacitance varying from 0.5 to 2 pF, when the TIA is used in optical sensing. In summary, the required very low input resistance, at a low input current level (µA) is achieved and furthermore a Table is included comparing the characteristics and a widely used Figure of Merit (FOM) for the proposed TIA and similar published low-power TIAs. It is apparent from the Table that the FOM of the proposed TIA is better than the FOMs of the other TIAs mentioned.

     

Optimal gate sizing using a self-tuning multi-objective framework

In this paper, we present a self-tuning multi-objective framework for geometric programming that provides a fine trade-off between the competing objectives. The significance of this framework is that the designer does not need to perform any tuning of weights of objectives. The proposed framework is applied to gate sizing and clock network buffer sizing problems. In gate sizing application, power consumption is reduced on average by 86% while delay sees only an increase of 34 ns. In clock network butter sizing application, our framework results in a significant reduction in power, 57%, and an improvement of 31 ps in skew.     

Novel CPG algorithm for tracking fast sudden changes based on tangent rule

ABSTRACT

This paper proposes a novel tracking method to deal with fast changes of solar irradiation and power limit change in order to increase tracking efficiency. This goal is achieved by estimating (i) next operating mode and (ii) next step point with the use of tangent rule in triangle. After every fast response to sudden changes, accurate response phase starts in order to track desired power in each operating mode by adaptive step size. Drift problem in defining next operating mode is eliminated in proposed method by estimating next operating mode, and settling time is decreased to about 25 percent of settling time of other methods by estimating next step point. Simulation and experimental results show the performance of proposed method.     

Low energy and area efficient quaternary multiplier with carbon nanotube field effect transistors

In this study, new multiplier and adder method designs with multiplexers are proposed. The designs are based on quaternary logic and a carbon nanotube field-effect transistor (CNTFET). The design utilizes 4 × 4 multiplier blocks. Applying specific rotational functions and unary operators to the quaternary logic reduced the power delay produced (PDP) circuit by 54% and 17.5% in the CNTFETs used in the adder block and by 98.4% and 43.62% in the transistors in the multiplier block, respectively. The proposed 4 × 4 multiplier also reduced the occupied area by 66.05% and increased the speed circuit by 55.59%. The proposed designs are simulated using HSPICE software and 32 nm technology in the Stanford Compact SPICE model for CNTFETs. The simulated results display a significant improvement in the fabrication, average power consumption, speed, and PDP compared to the current best-performing techniques in the literature. The proposed operators and circuits are evaluated under various operating conditions, and the results demonstrate the stability of the proposed circuits.     

Robust reservoir rock fracture recognition based on a new sparse feature learning and data training method

Multidimensional Systems and Signal Processing - In this paper, the main goal is to identify the sine fractures of reservoir rock automatically. Therefore, a five-step algorithm is applied on the...     

A New Approach to Analysis and Design of Chaos-Based Random Number Generators Using Algorithmic Converter

This paper presents a new approach to analysis and design of ADC-based random number generators. To this end, different full-bit and half-bit redundant stages of algorithmic converter are used to design chaotic maps. It is shown that, in the redundant and nonredundant structures, output probability density function of the converter stages and their related chaotic functions always converge to uniformity. It is demonstrated that residues become independent and uniformly distributed. This fact leads to the randomness and uniformity of distribution of the random number generator output bits. Moreover, it is shown that some common chaotic maps that are employed in chaotic random number generators can be implemented using nonredundant and half-bit redundant stages of algorithmic converter. In this way, the capability of ADC-based generators in designing chaotic maps and producing random number sequences is illustrated. The validity of the proposed chaos-based random number generator is confirmed using NIST statistical tests even in the presence of nonidealities in algorithmic converter. Since the ADCs are mixed-signal integrated circuits and can be used in high-speed applications, the ADC-based random number generator has high throughput and is easily embeddable in all analog and digital circuits.     

A FG-MOS Based Fully Differential Current Controlled Conveyor and Its Applications

This paper presents a new fully differential second generation current controlled conveyor (FDCCCII) based on differential pair topology, which employs floating gate MOS transistors (FG-MOS). It uses floating gate MOSFETs at the input stage and has rail-to-rail structure which performs with both positive and negative signals. This circuit has tunable parasitic resistance at its input port. It operates with low supply voltage (±0.8 V), low power consumption (lower than 3 mW at current bias of 1 mA), and wide range parasitic resistance (R _X ). This circuit has less MOSFET than the previous similar circuits and is suitable for integrated circuit design. To demonstrate the application of the proposed circuit, a fully differential current mode LC-ladder filter and a fully differential multifunction biquad filter are designed. Simulation results by HSPICE confirm validity of the proposed circuit and its application.     

All optical 2-bit analog to digital converter using photonic crystal based cavities

A novel design for realizing all optical analog to digital converter will be proposed in this paper. The proposed structure consists of two main parts; a nonlinear 3-channel demultiplexer, followed by an optical coder. The nonlinear demultiplexer will be used to quantize the input analog signal according to its optical intensity and the coder will convert the quantized levels into 2-bit binary codes. The nonlinear demultiplexer will be realized using three nonlinear resonant cavities. At appropriate values of input signal optical intensity one of the cavities can drop the optical beam to its corresponding output port. The proposed structure is capable of supporting maximum sampling rate up to 52 GS/s and total footprint of the structure is about 924 µm².     

A new true RMS-to-DC converter using up-down translinear loop in CMOS technology

In this paper a new true current-mode RMS-to-DC converter circuit based on a square-root-domain squarer/divider and simplified current-mode low pass filter is presented. The circuit is designed by employing up-down translinear loop and using of MOSFET transistors that operate in strong inversion saturation region. The converter offer advantages of two-quadrant input current, low circuit complexity, large dynamic range, low supply voltage (1.2 V) and immunity from the body effect. Moreover, the power consumption of the circuit for the maximum accepted input current is less than 100 μW and does not need extra biasing to inject current into transistors. The circuit has been simulated by HSPICE. The simulation results with 0.18 μm CMOS technology are seen to conform to the theoretical analysis and shows benefits of the proposed circuit. Simulation results show high performance of the proposed circuit.