Fast and Compact 16 by 16 Cellular Neural Network Implementation

The paper presents a Cellular Neural Network implementation based on a high gain sigmoid operation. The required simplifications to the original theory are described that allow the use of high gain. With this design black and white images can be processed. The basic building blocks in a cell are described. A 16×16 cells network has been designed and processed with 1.2 micron CMOS technology. Measurement results which show the operation of the network are presented.     

A Micropower Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer

In this paper, a micropower interface IC for a capacitive 3-axis micro-accelerometer implemented in a 0.13- BiCMOS process is presented. The sensor interface consists of a front-end that converts the acceleration signal to voltage, two algorithmic ADCs, two frequency references, and a voltage, current, and temperature reference circuit. Die area and power dissipation are reduced by using time-multiplexed sampling and varying duty cycles down to 0.3%. The chip with a 0.51 active area draws 62 from a 1.8 V supply while sampling temperature at 100 Hz, and four proof masses, each at 1.04 kHz. With a 4-g capacitive 3-axis accelerometer, the measured noise floors in the x-, y-, and z-directions are 482 , 639 , and 662 , respectively.     

A digital quadrature modulator with on-chip D/A converter

The first analog IF mixer stage of a transmitter can be replaced with this digital quadrature modulator. The modulator interpolates orthogonal input carriers by 16 and performs digital quadrature modulation at carrier frequencies f/sub s//4, -f/sub s//4,f/sub s//2 (f/sub s/ is the sampling frequency). A 12-b digital-to-analog (D/A) converter is integrated with the digital quadrature modulator. A segmented current source architecture is combined with a proper switching technique to reduce spurious components and to enhance dynamic performance. The digital quadrature modulator is designed to fulfill the spectral, phase, and EVM specifications of GSM, EDGE, and WCDMA base stations. The die area of the chip is 27.09 mm/sup 2/ (0.35-/spl mu/m CMOS technology) and the total power consumption is 1.02 W with 2.8 V at 500-MHz output sampling rate (0.78-W digital modulator, 0.24-W D/A converter).     

A single-chip multimode receiver for GSM900, DCS1800, PCS1900, and WCDMA

A single-chip, multimode receiver for GSM900, DCS1800, PCS1900, and UTRA/FDD WCDMA is introduced in this paper. The receiver operates at four different radio frequencies with two different baseband bandwidths. The presented chip uses a direct-conversion architecture and consists of a low-noise amplifier (LNA), downconversion mixers with on-chip local-oscillator I/Q generation, channel selection filters, and programmable gain amplifiers. In spite of four receive bands, only four on-chip inductors are used in the single-ended LNA. The repeatable receiver second-order input intercept point (IIP2) of over +42 dBm is achieved with mixer linearization circuitry together with a baseband circuitry having approximately +100-dBV out-of-band IIP2. The noise figure of the SiGe BiCMOS receiver is less than 4.8 dB in all GSM modes, and 3.5 dB in WCDMA. The power consumption from a 2.7-V supply in all GSM modes and in WCDMA mode is 42 and 50 mW, respectively. The silicon area is 9.8 mm/sup 2/ including the bonding pads.     

Temperature compensated logarithmic peak detector

A temperature compensated logarithmic amplifier for signal strength indicator or automatic gain control applications is presented. The logarithmic function is realized with a current-feedback operational amplifier with a nonlinear diode feedback. The designed BiCMOS current-feedback operational amplifier utilizes a novel circuit topology which makes possible constant 1 MHz bandwidth amplification with closed loop voltage gains up to 60 dB. The offset current of the current-feedback amplifier is cancelled with an active OTA-C feedback loop. The logarithmically amplified signal is further processed by a peak detector and a temperature compensation circuit. The temperature compensation principle is based on a division of two v _BE:s and it is realized with a current controlled variable current mirror. The logarithmic amplifier is fabricated with a 1.2 micron BiCMOS-process with NPN's f_T of 7 GHz. The power consumption of the circuit is 25 mW with a 4.5 V supply voltage.     

Mercerized cellulose biocomposites: a study of influence of mercerization on cellulose supramolecular structure, water retention value and tensile properties

In this study the effect of the mercerization degree on the water retention value (WRV) and tensile properties of compression molded sulphite dissolving pulp was evaluated. The pulp was treated with 9, 10, or 11 % aqueous NaOH solution for 1 h before compression molding. To study the time dependence of mercerization the pulp was treated with 12 wt% aqueous NaOH for 1, 6 or 48 h. The cellulose I and II contents of the biocomposites were determined by solid state cross polarization/magic angle spinning carbon 13 nuclear magnetic resonance (CP/MAS ¹³C NMR) spectroscopy. By spectral fitting of the C6 and C1 region the cellulose I and II content, respectively, could be determined. Mercerization decreased the total crystallinity (sum of cellulose I and cellulose II content) and it was not possible to convert all cellulose I to cellulose II in the NaOH range investigated. Neither increased the conversion significantly with 12 wt% NaOH at longer treatment times. The slowdown of the cellulose I conversion was suggested as being the result from the formation of cellulose II as a consequence of coalescence of anti-parallel surfaces of neighboring fibrils (Blackwell et al. in Tappi 61:71–72, 1978; Revol and Goring in J Appl Polym Sci 26:1275–1282, 1981; Okano and Sarko in J Appl Polym Sci 30:325–332, 1985). Compression molding of the partially mercerized dissolving pulps yielded biocomposites with tensile properties that could be correlated to the decrease in cellulose I content in the pulps. Mercerization introduces cellulose II and disordered cellulose and lowered the total crystallinity reflected as higher water sensitivity (higher WRV values) and poorer stiffness of the mercerized biocomposites.     

A Broadband Quadrature-Modulator in Standard 0.13 μm CMOS

A polyphase filtering topology is proposed which uses parallel switchable RC-networks for accurate broadband 90^∘ phasing. A 0.13μm CMOS prototype using the quadrature-generation network in a direct-conversion quadrature-modulator achieves a measured image-rejection ratio of −39 dBc or better in 0.6–2.5 GHz while consuming only 66 mW from a 2.2 V single supply. Esa Tiiliharjuwas born in Rovaniemi, Finland, in 1966. He received the M.Sc. degree in Information Technology in 1995, and the Lic.Tech degree in electrical engineering in 1998, both from Helsinki University of Technology, Finland. From 1996 to July 1997 he was employed as an assistant at Helsinki University of Technology. He has held a position as a research assistant since 1997, and he is currently working towards his Ph.D. degree in the Electronic Circuit Design Laboratory at Helsinki University of Technology. His research interests include the design of integrated low-power circuits for portable telecommunication applications. He has designed and measured several integrated circuits for this application area. He is the author or co-author of several internationally-refereed conference and journal publications on analog integrated circuits. Kari A.I. Halonenwas born in Helsinki, Finland, on May 23, 1958. He received the M.Sc. degree in electrical engineering from the Helsinki University of Technology (HUT) in 1982 and the Ph.D. degree in electrical engineering from the Katholieke Universiteit Leuven, Heverlee, Belgium, in 1987. From 1982 to 1984, he was with HUT as an Assistant and with the Technical Research Center of Finland as a Research Assistant. From 1984 to 1987, he was a Research Assistant with the E.S.A.T. Laboratory, Katholieke Universiteit Leuven, with a temporary grant from the Academy of Finland. Since 1988, he has been with the Electronic Circuit Design Laboratory, HUT, as a Senior Assistant from 1988 to 1990, and as the Director of the Integrated Circuit Design Unit of the Microelectronics Center from 1990 to 1993. He was on leave of absence during the academic year 1992–1993, acting as Research and Development Manager with Fincitec Inc., Finland. From 1993 to 1996, he was an Associate Professor, and since 1997, he has been a full Professor with the Faculty of Electrical Engineering and Telecommunications, HUT. He became the Head of Electronic Circuit Design Laboratory year 1998. He was the Technical Program Committee Chairman for the European Solid-State Circuits Conference in 2000. He is the author or coauthor of over 150 international and national conference and journal publications on analog integrated circuits, and holds several patents on analog integrated circuits. His research interests are in CMOS and BiCMOS analog integrated circuits, particularly for telecommunication applications. Dr. Halonen was an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–PART I: FUNDAMENTAL THEORY AND APPLICATIONS from 1997 to 1999. He has been a Guest Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS. He received the BeatriceWinner Award from the IEEE International Solid-State Circuits Conference in 2002.[c-halonen.eps]     

A Self-Calibrated Pipeline ADC with 200 MHz IF-Sampling Frontend

A 13-bit, 50-MS/s pipeline ADC with IF-sampling capability is presented. A high sampling linearity is obtained through the use of bootstrapped switches. A digital self-calibration algorithm with modified capacitor measurement scheme is employed to improve the accuracy of the first two pipeline stages. The prototype, implemented with a 0.35-m BiCMOS (SiGe) technology, shows a 76.5-dB SFDR at a 194.2-MHz signal frequency and dissipates 715 mW power from a 2.9-V supply.     

80-MHz bandpass /spl Delta//spl Sigma/ modulators for multimode digital IF receivers

Three fully differential bandpass (BP) /spl Delta//spl Sigma/ modulators are presented. Two double-delay resonators are implemented using only one operational amplifier. The prototype circuits operate at a sampling frequency of 80 MHz. The BP /spl Delta//spl Sigma/ modulators can be used in an intermediate-frequency (IF) receiver to combine frequency downconversion with analog-to-digital conversion by directly sampling an input signal from an IF of 60 MHz to a digital IF of 20 MHz. The measured peak signal-to-noise-plus-distortion ratios are 78 dB for 270 kHz (GSM), 75 dB for 1.25 MHz (IS-95), 69 dB for 1.762 MHz (DECT), and 48 dB for 3.84 MHz (WCDMA/CDMA2000) bandwidths. The circuits are implemented with a 0.35-/spl mu/m CMOS technology and consume 24-38 mW from a 3.0-V supply, depending on the architecture.