High Rate Data Synchronization in GALS SoCs

Globally asynchronous, locally synchronous (GALS) systems-on-chip (SoCs) may be prone to synchronization failures if the delay of their locally-generated clock tree is not considered. This paper presents an in-depth analysis of the problem and proposes a novel solution. The problem is analyzed considering the magnitude of clock tree delays, the cycle times of the GALS module, and the complexity of the asynchronous interface controllers using a timed signal transition graph (STG) approach. In some cases, the problem can be solved by extracting all the delays and verifying whether the system is susceptible to metastability. In other cases, when high data bandwidth is not required, matched-delay asynchronous ports may be employed. A novel architecture for synchronizing inter-modular communications in GALS, based on locally delayed latching (LDL), is described. LDL synchronization does not require pausable clocking, is insensitive to clock tree delays, and supports high data rates. It replaces complex global timing constraints with simpler localized ones. Three different LDL ports are presented. The risk of metastability in the synchronizer is analyzed in a technology-independent manner     

Delaunay graphs are almost as good as complete graphs

LetS be any set ofN points in the plane and let DT(S) be the graph of the Delaunay triangulation ofS. For all pointsa andb ofS, letd(a, b) be the Euclidean distance froma tob and let DT(a, b) be the length of the shortest path in DT(S) froma tob. We show that there is a constantc (≤((1+√5)/2) π≈5.08) independent ofS andN such that $$\frac{{DT(a,b)}}{{d(a,b)}}< c.$$      

On sparse spanners of weighted graphs

Given a graphG, a subgraphG' is at-spanner ofG if, for everyu,v V, the distance fromu tov inG' is at mostt times longer than the distance inG. In this paper we give a simple algorithm for constructing sparse spanners for arbitrary weighted graphs. We then apply this algorithm to obtain specific results for planar graphs and Euclidean graphs. We discuss the optimality of our results and present several nearly matching lower bounds.The work of G. Das and D. Joseph was supported by NSF PYI Grant DCR-8402375. The work of D. Dobkin was supported by NSF Grant CCR-8700917. The work of J. Soares was supported by CNPq proc 203039/87.4 (Brazil) and NSF Grant CCR-9014562. This research was accomplished while G. Das was a student at the University of Wisconsin-Madison. A preliminary version was presented at the Second Scandinavian Workshop on Algorithm Theory, Bergen, Norway, 1990, under the title Generating Sparse Spanners for Weighted Graphs, and proceedings appear in the series Lecture Notes in Computer Science, Springer-Verlag. The preliminary version also appears as Princeton University Technical Report CS-TR-261-90, and as University of Wisconsin-Madison Computer Sciences Technical Report 882.     

用于电压或电流调节的新调节器架构

一种新的调节器架构为分散热量和电流调节提供了解决方案。这些新的调节器具有优于从前器件的性能。     

Efficient uses of the past

Existing data structures for maintaining sets do not remember the situation they represented at previous times. We propose a structure from which it is possible to efficiently reconstruct the state of the data it represented at any time. Applications of this data structure to several important problems in geometric computation are also given.     

Catalytic Halocarbon Decomposition in a Microwave Post-discharge

Plasma Chemistry and Plasma Processing - A computer simulation of chemical, charged-particle, and excited-particle kinetics in a microwave post-discharge in humid air with halocarbon (CCl3F) traces...     

StarSync: An extendable standard-cell mesochronous synchronizer

StarSync, a mesochronous synchronizer, enables low latency and full throughput crossing of clock domain boundaries having same frequency but different phases. Full back pressure is supported, where the receiver can start and stop accepting words without any data loss. Variable depth buffering is provided, supporting a wide range of short and long range communications and accommodating multi-cycle wire delays. Burst data can also be accommodated thanks to buffering. Dynamic phase shifting due to varying voltage and temperature are mitigated by increasing the separation between write and read pointers. The synchronizer is exposed to metastability risk only during reset. It is suitable for implementation using standard cell design and requires neither delay lines nor other full custom circuits. It is shown that a minimum of four buffer stages are required, to mitigate skew in reset synchronization, in contrast with previous proposals for three stages.