A VLSI CMOS delay oriented waveform converter for polyphasefrequency synthesizer

In this paper, we present a waveform converter implemented on a 0.25-μm CMOS technology using a dedicated design methodology (Delay Oriented Design). The circuit converts a square wave signal in both in-phase and quadrature-phase sinusoidal differential outputs. It also multiplies the frequency by seven. The output frequency range of this converter extends from 1.05 GHz up to 2.17 GHz. This converter is dedicated for the design of a third-generation mobile phone synthesizer using a double-loop architecture. For an output frequency of 2 GHz, the measured phase noise at 10-kHz offset from the carrier is -97 dBc/Hz. The circuit consumes 50 mW from a 2.5-V supply     

RF CMOS body-effect circuits

After a theoretical and analytical study of the body effect in MOS transistors, this paper offers two useful models of this parasitic phenomenon. Thanks to these models, a design methodology, which takes advantage of the bulk terminal, allows to turn this well-known body-effect drawback into an analog advantage, giving thus an efficient alternative to overcome the design constraints of the CMOS VLSI wireless mass market. To illustrate the approach, four RF building blocks are presented. First, a 0.9 V 10 dB gain LNA, covering a frequency range 1.8-2.4 GHz, thanks to a body-effect common mode feedback, is detailed. Secondly, a body-effect linearity controlled pre-power amplifier is presented exhibiting a 5 dB m input compression point (ICP1) variation under 1.8 V power supply for half the current consumption. Lastly, two mixers based on body-effect mixing are presented, which achieve a 10 dB conversion gain under 1.4 V for a −52 dB LO-to-RF isolation. Well suited for low-power/low-voltage applications, these circuits implemented in a 0.18 μm CMOS VLSI technology are dedicated to multi-standard architectures and system-on-chip implementations.     

A low-power 1-GHz super-regenerative transceiver with time-sharedPLL control

A low-power transceiver for ISM applications in the 868-MHz band has been integrated in a 0.8-μm BiCMOS technology. The receiver part is based on the super-regenerative principle. The system includes two time-shared control loops, one for the selectivity and sensitivity control and one for the frequency control (PLL). The receiver with its PLL draws 3.6 mW for a sensitivity of -105 dBm and the emitter current consumption is 6 mA for a 0-dBm output power. A 2.4-V operation voltage allow the use of a two-batteries solution     

HiperLAN 5.4-GHz low-power CMOS synchronous oscillator

A 5.4-GHz 0.25-μm very-large-scale-integration CMOS synchronous oscillator (SO) is proposed in this paper, which is designed to act as a local oscillator for HiperLAN systems. The advantage of using such an oscillator in a double-loop frequency synthesizer is demonstrated. The design strategy leading to an optimized SO with regards to its synchronization range is described. A test chip is presented, which provides a 150-MHz synchronization range and a -97-dBc/Hz phase noise at 10-kHz offset from the 5-GHz carrier, while consuming only 5 mA from a 2.5-V supply     

Top-down design methodology of a multi-bit continuous-time delta–sigma modulator

Transistor-level simulation of complex systems involving analog and digital parts is a time-consuming task. The growing interaction of analog and digital devices calls for the use of top-down design methodologies, resulting in behavioral modeling at different levels of abstraction. In this article, an advanced design methodology using a combination of behavioral models and transistor-level models is presented. This methodology is very interesting for complex mixed-signal IC design, improving the design flexibility and reducing the simulation time. To validate the proposed methodology, a continuous-time delta–sigma modulator based on a high-speed low-resolution quantizer is modeled, taking into account their nonidealities such as excess loop delay, clock jitter and feedback DAC element mismatch. The main features of the multi-bit quantizer are 3-bit resolution with 4 GHz sampling rate and FOM of about 7 pJ/conv. This modulator samples signals at high-IF, performing directly the analog-to-digital conversion in the modern RF front-end receivers.     

Evaluation of physical carrier sense based spanner construction and maintenance as well as broadcast and convergecast in ad hoc networks

While the use of physical carrier sensing for medium access control in ad hoc wireless networks is well established, exploiting physical carrier sensing directly for network layer functions is largely unexplored. We conduct extensive simulation evaluations of recently proposed algorithms that directly exploit physical carrier sensing for backbone network (spanner) construction, broadcast, and convergecast in wireless ad hoc networks. Our algorithms accommodate interference ranges larger than transmission ranges, explicitly incorporate the medium access control and packet collisions, and do not require any prior knowledge of the network. For spanner construction, our algorithms include three self-stabilizing phases that establish leader nodes able to reach all nodes in one hop, assign the leaders non-interfering transmission rounds, and connect the leaders through gateway nodes. We evaluate the backbone construction and maintenance as well as broadcast and convergecast through simulations. We find that over 75% of the control messages for backbone network construction are received from physical carrier sensing. While the number of backbone nodes is relatively large, the backbone is very robust, quickly self-stabilizing, and only a fraction of the backbone nodes are used for broadcast.     

Novel CMOS pipelined A/D convertor architecture using current mirrors

A novel current source-based CMOS pipelined A/D convertor architecture is presented. Compared to previous switched-capacitor realisations, the proposed architecture offers significant advantages in terms of power consumption, accuracy, simplicity and silicon area.<>     

A high-efficiency CMOS voltage doubler

A charge pump cell is used to make a voltage doubler using improved serial switches. A complete power efficiency theory is presented which fits the measurements. The importance of capacitors is shown with plots of power efficiency versus load and stray capacitors. Several problems arising at low voltage or high frequency are developed and some optimizations are presented. The substrate current is totally suppressed by the technique of bulk commutation. A power efficiency of 95% has been reached using external capacitors. A fully integrated charge pump is also presented and shows a maximum power efficiency of 75%     

Design of a high-speed CMOS multi-bit quantizer for continuous-time Delta-Sigma Modulator applications

Digital front-end receivers realize direct conversion of an analog signal to digital form at intermediate frequencies (IF), simplifying the overall system design and alleviating the problems associated with IF mixers. The trend is to eliminate any RF/analog mixers and digitize the RF signal as near as possible to the antenna. In order to digitize directly the analog input signal, a high dynamic-range and high-speed ADC is needed. Continuous-Time Bandpass Delta-Sigma Modulator can meet these requirements, using high-performance multi-bit quantizers. This article presents the design of a high-speed CMOS Analog-to-Digital Converter (ADC) which can be used as a quantizer in Continuous-Time Delta-Sigma Modulator. It is designed in a 130 nm CMOS technology from STMicroelectronics. The main features of the ADC are 3-bit resolution with 4 GHz sampling rate in a 0.8–2 GHz bandwidth.