A 54-MHz CMOS programmable video signal processor for HDTVapplications

A 54-MHz CMOS video processor with a systolic architecture suited for two-dimensional symmetric FIR (finite impulse response) filtering is reported. The circuit is a one-dimensional digital filter comprising a control part and an array of eight multiplication-accumulation cells. This processor is capable of handling 32 equivalent multiply-add operations in a sampling period as short as 18 ns. Devices can be cascaded to increase the order of the filter in both dimensions, up to 1024 stages with no truncation errors. It has been developed in a 1.2-μm CMOS technology, and it dissipates less than 500 mW at a 54-MHz clock frequency     

Optical Thomson scattering measurements of plasma parameters in the ablation stage of wire array Z pinches

A Thomson scattering diagnostic has been used to measure the parameters of cylindrical wire array Z pinch plasmas during the ablation phase. The scattering operates in the collective regime (α>1) allowing spatially localized measurements of the ion or electron plasma temperatures and of the plasma bulk velocity. The ablation flow is found to accelerate towards the axis reaching peak velocities of 1.2-1.3×10(7) cm/s in aluminium and ～1×10(7) cm/s in tungsten arrays. Precursor ion temperature measurements made shortly after formation are found to correspond to the kinetic energy of the converging ablation flow.     

The implementation of P3I, a parallel architecture forvideo real-time processing: a case study

This paper provides a tutorial on the motivations, design, and applications of parallel processing applied to video real-time, illustrated by the experience gained in the implementation of the P³I machine. Its main purpose is to highlight the motivations for such a development the basic implementation choices, the major difficulties encountered and how they have been solved. Through these studies we found that parallel processing is well-suited to video real-time, when programmable implementations are considered. There are many outcomes of the P³I project, ranging from architectural considerations to parallel algorithms optimizations, and programming methodology. We want to emphasize three conclusions. First, programming an architecture composed of different parallel paradigms in a given architecture is tractable, and this heterogeneity is cost effective and efficient in terms of processing performances. Second, concerning the well known debate about how to match parallel architectures and image processing “levels” we conclude that the key is not to discuss Flynn's taxonomy (i.e., data versus tasks parallelism) but to consider how the parallelism grain evolves within a whole application. Third, we confirm that in the field of image processing, the efficiency of parallelism can only be gained if algorithms developers think “parallel”; this result seems to be obvious, but just consider the trends of recent RISC processors, embedding more and more parallelism, and claiming at a compatibility with existing sequential softwares