Cost-effective smart power CMOS/DMOS technology: design methodology for latch-up immunity

To answer to the need of a cost effective smart power technology, an original design methodology that permits implementing latch-up free smart power circuits on a very simple CMOS/DMOS technology is proposed. The basic concept used to this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up. The efficiency of the design methodology is experimentally shown.     

A 0.9-V microcontroller for portable applications

A 0.9-1.6-V, 1-MHz, 8-b microcontroller based on the 68HC08 architecture is presented. In addition to standard digital microcontroller functions, the chip features RAM, ROM, phase-locked loop (PLL) clock synthesis, and liquid crystal displays (LCD) drive capabilities operating from the voltage supply range of a single AA or AAA battery. The design used a library of CMOS microcontroller building blocks, converted into a low-voltage technology using unilateral transistors. The design approach was to optimize the conversion strategy for each functional block and to provide new designs when the conversion was insufficient. The chip exceeded specifications with blocks showing full functionality down to 0.7 V     

Planar-transistor stability under X ray irradiation

Experiments on planar transistors irradiated by X rays show drifts of variable importance, according to the type of transistor (p-n-p or n-p-n). As an interpretation of the results, surface-characteristic modification of the e-b diode due to the presence of a silicon-surface-induced charge density is proposed.     

Application of a floating well concept to a latch-up-free,low-cost, smart power high-side switch technology

An original design methodology that permits implementing latch-up-free smart power circuits on a very simple, cost-effective technology is presented. The basic concept used for this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up     

Physical macromodelling of the dynamic behaviour of CMOS VLSI circuits: Part II

In a companion paper [1], a physical model of the dynamic behaviour of a CMOS inverter, based on the physical analysis of the switching mechanism, was presented. The accuracy of this model was shown to be virtually the same as that obtained with SPICE. The aim of this paper is the application of this analytical model to the derivation of circuit-level and logic-level models for complex gates through the definition of an equivalent inverter for each gate and each active transition. These models were implemented in a mixed-level simulator, CINNAMON [2], and were shown to bring about a similar accuracy as that obtained with SPICE, whereas the necessary CPU time was improved by two orders of magnitude.     

Cost-effective smart power CMOS/DMOS technology: design of main driving and protection functions

This paper intends to show that even with a CMOS technology main driving and protection functions of a power VDMOS can be made performant. Original circuits taking advantage of the availibility of the parasitic vertical bipolar transistor are presented and experimentally evaluated. A current mode approach is proposed to improve the accuracy of the current sensing function aimed at performing overcurrent, short-circuit and open-load detection.     

Degradation mechanism of m.o.s. structures and transistors under ionising radiation

The physical nature of the emission-current mechanism involved at each heterojunction when m.o.s. components are irradiated is discussed by the authors. They test the validity of this mechanism with an overall experiment, and analyse its practical consequences on the form of the ?VG(VG) degradation curve.