Some extremal problems for functions of bounded boundary rotation

A variational method is developed within the class of functions of boundary rotation not exceedingkπ which is based on the fact that the set of representing measuresμ is convex. It shows that an extremal problem related to a functional with Gateaux derivative and some constraints leads to extremal measuresμ ₀ with finite support. The positive and negative part of aμ ₀ is located at points where a functionJ (depending onμ ₀) reaches its maximum and minimum respectively. The method is tested successfully on various problems.     

Approaches to the Synthesis of Cytochalasans. Part 11. Further transformations and cyclization attempts directed towards proxiphomin

Starting from iodoalcohol 9 , the monoprotected dialdehyde 5 was synthesized (Scheme 2) and converted to 17 by reaction with oxo-phosphonate 15 (Scheme 3). The latter was prepared from 13 . Cyclisation of 17 to the target compound 18 failed. Also the attachment of thiol 22 to lactone 19 was unsatisfactory (Scheme 4). Therefore, the building blocks 28 and 29 were synthesized using diene 33 and diester 30 as starting material for 28 and 9 for 29 (Scheme 5 and 6). Hydroxy acid 28 was converted into formyl-ester 46 (Scheme 7). However, the condensation of its derivatives 48 and 49 with ‘Umpolung’ of the carbonyl reactivity was unsuccessful, probably due to steric hindrance.     

Digital Predistortion for 5G Small Cell: GPU Implementation and RF Measurements

In this paper, we present a high data rate implementation of a digital predistortion (DPD) algorithm on a modern mobile multicore CPU containing an on-chip GPU. The proposed implementation is capable of running in real-time, thanks to the execution of the predistortion stage inside the GPU, and the execution of the learning stage on a separate CPU core. This configuration, combined with the low complexity DPD design, allows for more than 400 Msamples/s sample rates. This is sufficient for satisfying 5G new radio (NR) base station radio transmission specifications in the sub-6 GHz bands, where signal bandwidths up to 100 MHz are specified. The linearization performance is validated with RF measurements on two base station power amplifiers at 3.7 GHz, showing that the 5G NR downlink emission requirements are satisfied.

     

A Low-overhead Scheduling Methodology for Fine-grained Acceleration of Signal Processing Systems

Fine-grained accelerators have the potential to deliver significant benefits in various platforms for embedded signal processing. Due to the moderate complexity of their targeted operations, these accelerators must be managed with minimal run-time overhead. In this paper, we present a methodology for applying flow-shop scheduling techniques to make effective, low-overhead use of fine-grained DSP accelerators. We formulate the underlying scheduling approach in terms of general flow-shop scheduling concepts, and demonstrate our methodology concretely by applying it to MPEG-4 video decoding. We present quantitative experiments on a soft processor that runs on a field-programmable gate array, and provide insight on trends and trade-offs among different flow-shop scheduling approaches when applied to run-time management of fine-grained acceleration.     

Quasi-Static Scheduling of CAL Actor Networks for Reconfigurable Video Coding

The upcoming Reconfigurable Video Coding (RVC) standard from MPEG (ISO / IEC SC29WG11) defines a library of coding tools to specify existing or new compressed video formats and decoders. The coding tool library has been written in a dataflow/actor-oriented language named CAL. Each coding tool (actor) can be represented with an extended finite state machine and the data communication between the tools are described as dataflow graphs. This paper proposes an approach to model the CAL actor network with Parameterized Synchronous Data Flow and to derive a quasi-static multiprocessor execution schedule for the system. In addition to proposing a scheduling approach for RVC, an extension to the well-known permutation flow shop scheduling problem that enables rapid run-time scheduling of RVC tasks, is introduced.     

Toward Efficient Execution of RVC-CAL Dataflow Programs on Multicore Platforms

The increasing number of cores in System on Chips (SoC) has introduced challenges in software parallelization. As an answer to this, the dataflow programming model offers a concurrent and reusability promoting approach for describing applications. In this work, a runtime for executing Dataflow Process Networks (DPN) on multicore platforms is proposed. The main difference between this work and existing methods is letting the operating system perform Central processing unit (CPU) load-balancing freely, instead of limiting thread migration between processing cores through CPU affinity. The proposed runtime is benchmarked on desktop and server multicore platforms using five different applications from video coding and telecommunication domains. The results show that the proposed method offers significant improvements over the state-of-art, in terms of performance and reliability.