A 16-Mbit/s adapter chip for the IBM token-ring local area network

The authors describe a 9.02×9.02-mm chip built in 1-μm CMOS with two levels of metal and an additional mask level for fabricating capacitors. It contains both analog and digital circuits and has provisions for self-test. The function includes the transmitter, receiver, protocol handler, an microprocessor, as well as interfaces for RAM/ROM storage, IBM PC bus, IBM PS/2 bus, IBM 3174 bus, and Motorola 68000 bus. The physical design terrains are formed by 24K circuits of standard cell gates, a 10K-circuit equivalent hand-honed custom microprocessor, and an analog macro. The chip operates from a single 5-V supply, and the power consumption is 0.8 W nominal at 16 Mb/s. The chip can also be operated at 4 Mb/s     

Comment on new differential flip-flops from Yuan and Svensson

A family of differential latches has recently been proposed by Yuan and Svensson [1996]. The author shows that the proposed flip-flops using the dynamic slave latch suffer from a poor logic-level zero in the presence of glitches on the data inputs     

A closed-form representation of mixed-integer program value functions

We identify a class of formulas computable in polynomial time such that the functions defined by these formulas are precisely the value functions of mixed-integer programs with rational constraint coefficients.