Cost-effective smart power CMOS/DMOS technology: design methodology for latch-up immunity

To answer to the need of a cost effective smart power technology, an original design methodology that permits implementing latch-up free smart power circuits on a very simple CMOS/DMOS technology is proposed. The basic concept used to this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up. The efficiency of the design methodology is experimentally shown.     

TCAD and SPICE modeling help solve ESD protection issues in analog CMOS technology

The number of circuit design iterations due to electrostatic discharge (ESD) failures increases with the complexity of VLSI technologies and their shrinking. In this paper, we show how TCAD and ESD SPICE modeling can be used to solve ESD protection issues in an analog CMOS technology.     

Size Effect on Properties of Varistors Made From Zinc Oxide Nanoparticles Through Low Temperature Spark Plasma Sintering

Conditions for the elaboration of nanostructured varistors by spark plasma sintering (SPS) are investigated, using 8‐nm zinc oxide nanoparticles synthesized following an organometallic approach. A binary system constituted of zinc oxide and bismuth oxide nanoparticles is used for this purpose. It is synthesized at room temperature in an organic solution through the hydrolysis of dicyclohexylzinc and bismuth acetate precursors. Sintering of this material is performed by SPS at various temperatures and dwell times. The determination of the microstructure and the chemical composition of the as‐prepared ceramics are based on scanning electron microscopy and X‐ray diffraction analysis. The nonlinear electrical characteristics are evidenced by current–voltage measurements. The breakdown voltage of these nanostructured varistors strongly depends on grain sizes. The results show that nanostructured varistors are obtained by SPS at sintering temperatures ranging from 550 to 600 °C.     

Potentialities of substrate-thinning technique to control minority carrier injection in smart power IC's

This paper deals with the evaluation of a substrate-thinning technique as a way to control the substrate current issues. A test structure has been realized on a Smart Power Technology. Comprehension of the phenomena has been validated thanks to TCAD simulation. This technique was then applied to a commercial IC and the authors show that they succeeded to reduce by one decade the collected current on a victim, although the IC has already been optimized with classical solutions.     

Long-term reliability of silicon bipolar transistors subjected to low constraints

We present in this study the effect of electrical ageing on silicon (Si) NPN bipolar transistors. This study is based on a sample of half-hundred components, which have been fabricated in the early 1980s, which represents an exceptional experience feedback. By means of static and low frequency noise measurements, which are used as diagnostic tools for reliability assessment, we have noticed a good accordance with a physical model based on an oxide charge modulation. We have also used emission microscopy and electron beam-induced current analysis in order to visualize and to localize the defects in the structure. These have been located in the spacer oxide at the periphery of the base-emitter junction.     

Analysis and compact modeling of a vertical grounded-base n-p-nbipolar transistor used as ESD protection in a smart power technology

A thorough analysis of the physical mechanisms involved in a vertical grounded-base n-p-n bipolar transistor (VGBNPN) under electrostatic discharge (ESD) stress is first carried out by using two-dimensional (2-D) device simulation, transmission line pulse measurement (TLP) and photoemission experiments. This analysis is used to account for the unexpected low value of the VGBNPN snapback holding voltage under TLP stress. A compact model based on a new avalanche formulation resulting from the exact resolution of the ionization integral is therefore proposed     

Implementation of Thermoelectric Generators in Airliners for Powering Battery-Free Wireless Sensor Networks

In recent years, wireless sensor networks (WSN) have been considered for various aeronautical applications to perform sensing, data processing and wireless transmission of information, without the need to add extra wiring. However, each node of these networks needs to be self-powered. Considering the critical drawbacks associated with the use of electrochemical energy sources such as narrow operating temperature range and limited lifetime, environmental energy capture allows an alternative solution for long-term, deploy and forget, WSN. In this context, thermoelectricity is a method of choice considering the implementation context. In this paper, we present hands-on experience related to on-going implementations of thermoelectric generators (TEG) in airliners. In a first part, we will explain the reasons justifying the choice of ambient energy capture to power WSN in an aircraft. Then, we will derive the general requirements applying to the functional use of TEG. Finally, in the last section, we will illustrate the above issues through practical implementations.     

Application of a floating well concept to a latch-up-free,low-cost, smart power high-side switch technology

An original design methodology that permits implementing latch-up-free smart power circuits on a very simple, cost-effective technology is presented. The basic concept used for this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up     

Physical macromodelling of the dynamic behaviour of CMOS VLSI circuits: Part II

In a companion paper [1], a physical model of the dynamic behaviour of a CMOS inverter, based on the physical analysis of the switching mechanism, was presented. The accuracy of this model was shown to be virtually the same as that obtained with SPICE. The aim of this paper is the application of this analytical model to the derivation of circuit-level and logic-level models for complex gates through the definition of an equivalent inverter for each gate and each active transition. These models were implemented in a mixed-level simulator, CINNAMON [2], and were shown to bring about a similar accuracy as that obtained with SPICE, whereas the necessary CPU time was improved by two orders of magnitude.     

Design and applications of an easily integrable CMOS operational floating amplifier for the MegaHertz range

The design and major applications of a general purpose current mode building block are presented in this paper. This circuit is basically a high gain transconductance scheme with differential current output terminals previously termed operational floating amplifier (OFA). The novel structure proposed here is shown to implement a very flexible and high performance amplifier which can be used in almost all applications employing conveyors, current feedback amplifiers or even conventional operational amplifiers with improved performance characteristics. This presentation is also supported by experimental measurements on a prototype circuit realized in CMOS technology.