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A novel voltage-controlled oscillator(VCO) topology with low voltage and low power is presented. It employed the inductive-biasing to build a feedback path between the tank and the MOS gate to enhance the voltage gain from output nodes of the tank to the gate node of the cross-coupled transistor. Theoretical analysis using timevarying phase noise theory derives closed-form symbolic formulas for the 1/f~2 phase noise region, showing that this feedback path could improve the phase noise performance. The proposed VCO is fabricated in TSMC 0.13 m CMOS technology. Working under a 0.3 V supply voltage with 1.2 m W power consumption, the measured phase noise of the VCO is –119.4 d Bc/Hz at 1 MHz offset frequency from the carrier of 4.92 GHz, resulting in an Fo M of 192.5 d Bc/Hz. 相似文献
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一种新型超宽带单极子缝隙天线设计与仿真 总被引:1,自引:1,他引:0
提出了一种新型超宽带单极子缝隙天线,该天线包含一个类似于单极子天线的缝隙和叉状共面波导馈电结构,蚀刻在FR4-PCB板上,尺寸为26 mm×26 mm×1.4 mm。该天线采用HFSS13.0软件进行仿真,并对天线模型参数进行优化。结果表明:该天线具有良好的阻抗匹配和方向图特性,频带宽度为2.53~19.30 GHz(S11≤–10 d B),相对带宽达到154%,满足超宽带天线要求。 相似文献
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A non-coherent receiver for impulse radio ultra-wide band(IR-UWB)is presented.The proposed receiver front-end consists of a high gain LNA,a high frequency detector and an intermediate frequency(IF)amplifier to amplify the recovered signal and drive an external test instrument.To meet the requirements of high gain and a low noise figure(NF)under moderate power consumption for the LNA,capacitor cross coupled(CCC)and current reuse techniques were adopted.The detector consists of a squarer and an integrator.The overall circuit consumes 41.2mA current with a supply voltage of 1.8 V at a 400 MHz pulse rate.The resulting energy efficiency is 0.19 nJ/pulse.A chip prototype is implemented in 0.18-μm CMOS.The die area is 2.1×1.4 mm~2 and the active area is 1.7×0.98 mm~2. 相似文献
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本文提出了一个高性能的正交振荡器。该振荡器采用具有顶层厚金属的SMIC CMOS 0.18um工艺实现。采用cascode串联耦合来产生正交信号。对NMOS差分对管引入源级退化电容来抑制其1/f噪声转化为振荡器的近端相位噪声。并最终采用专用的低噪声,高电源抑制能力的LDO来供电。正交振荡器测试显示4.78GHz信号输出时1MHz频偏处相位噪声-123.3dBc/Hz.频率范围为4.09GHz到4.87GHz,17.5%的调谐范围。调谐增益在44.5MHz/V至66.7MHz/V之间。核心芯片面积不包含pad和ESD保护电路的为0.41mm2。 相似文献
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基于华润上华0.5 μm双极-CMOS-DMOS (BCD)工艺设计制备了不同保护环分布情况下的叉指型内嵌可控硅整流器的横向扩散金属氧化物半导体(LDMOS-SCR)结构器件,并利用传输线脉冲(TLP)测试比较静电放电(ESD)防护器件的耐压能力.以LDMOS-SCR结构为基础,按照16指、8指、4指和2指设置保护环,形成4种不同类型的版图结构.通过器件的直流仿真分析多指器件的开启情况,利用传输线脉冲测试对比不同保护环版图结构的耐压能力.仿真和测试结果表明,改进后的3类版图结构相对于普遍通用的第一类版图结构,二次击穿电流都有所提升,其中每8指设置一个保护环的版图结构二次击穿电流提升了76.36%,其单位面积的鲁棒性能也最好,为相应工艺设计最高耐压值的ESD防护器件提供了参考结构和方法. 相似文献
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A high performance quadrature voltage-controlled oscillator(QVCO) is presented.It has been fabricated in SMIC 0.18μm CMOS technology with top thick metal.The proposed QVCO employed cascade serial coupling for in phase and quadrature phase signal generation.Source degeneration capacitance is added to the NMOS differential pair to suppress their flicker noise from up-conversion to close in phase noise.A dedicated low noise and high power supply rejection low drop out regulator is used to supply this QVCO.The measured phase noise of the proposed QVCO achieves phase noise of-123.3 dBc/Hz at an offset frequency of 1 MHz from the carrier of 4.78 GHz,while the QVCO core circuit and LDO draw 6 mA from a 1.8 V supply.The QVCO can operate from 4.09 to 4.87 GHz(17.5%).Measured tuning gain of the QVCO(Kvco) spans from 44.5 to 66.7 MHz/V.The chip area excluding the pads and ESD protection circuit is 0.41 mm2. 相似文献
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一种模数转换器的采样保持/增益减法电路设计 总被引:3,自引:3,他引:0
文章介绍了一种适用于算法型流水线模数转换器(Pipeline ADC)的CMOS全差分采样保持/减法增益电路的设计。该电路的工作电压为3V,在70MHz的采样频率下可达到10位以上的精度:调节型共源共栅运算放大器可在不增加更多的级联器件的情况下就可以获得很高的增益及很大的输出阻抗:专为算法型模数转换器设计的采样保持/增益减法电路通过时序控制可实现校准状态和正常转换状态的转换:通过底极板采样技术和虚拟器件有效地消除了电荷注入及时钟馈通。最后用HSPICE仿真,证明其适用于10bit及以上精度的算法型流水线模数转换器。 相似文献