应用于千兆以太网的1-Gb/s 零极点对消CMOS跨阻放大器

A zero-pole cancellation transimpedance amplifier（TIA）has been realized in 0.35μm RF CMOS technology for Gigabit Ethernet applications.The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration.Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ωfor 1.5 pF photodiode capaci- tance,with a gain-bandwidth product of 3.4 THz·Ω.Even with 2 pF photodiode capacitance,the bandwidth exhibits a decline of only 300 MHz,confirming the mechanism of the zero-pole cancellation configuration.The input resis- tance is 50Ω,and the average input noise current spectral density is 9.7 pA/√ Hz.Testing results shows that the eye diagram at 1 Gb/s is wide open.The chip dissipates 17 mW under a single 3.3 V supply.     

A 900 MHz fractional-N synthesizer for UHF transceiver in 0.18μm CMOS technology

A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16(24)sub-bands. A 7/8 dual-modulus prescaler is implemented with a phase-switching circuit and high-speed flip–flops, which are composed of source coupled logic. The proposed synthesizer phase-locked loop is demonstrated with a 50 k Hz band width by a low 12.95 MHz reference clock, and offers a better phase noise and band width tradeoff. To reduce the out-band phase noise, a 4-levels 3-order single-loop sigma–delta modulator is applied. When its relative frequency resolution is settled to 10-6, the testing results show that the phase noises are –120.6 d Bc/Hz at 1 MHz and –95.0 d Bc/Hz at 100 k Hz. The chip is2.1 mm2 in UMC 0.18μm CMOS. The power is 36 m W at a 1.8 V supply.     

高性能硅基MOS电光相位调制器

提出了一种SOI新型MOS电容型电光调制器.与普通单一电容型MOS调制器相比,由三层栅氧化层形成的新型MOS电容型调制器提高了调制效率.模拟显示,调制电压和调制长度乘积为VπLπ=2.4V·cm,上升和下降时间分别为80和40ps,带宽达到了8GHz.通过减小器件尺寸能进一步提高调制效率和调制速度.     

用于神经记录的低功耗CMOS前置放大器

本文提出了一种应用于胞外神经记录的全差分带通CMOS前置放大器。这种放大器采用“容性耦合结合容性反馈”式拓扑结构。放大器具有20.4 dB的中带增益,且无直流增益。高频-3 dB截止频率为6.7 KHz,而低频-3 dB截止频率可根据不同频段场电位或动作电位的放大需求作出调整。在3.3 V供电下,放大器的通带设置为0.15 Hz到6.7 KHz（可同时记录本地场电位和神经元峰电位）,测得输入参考噪声为8.2 μVrms,功耗仅为23.1 μW。文中也设计了为前置放大器提供偏置电压和偏置电流的带隙参考电路。该原型芯片基于0.35-μm N阱CMOS 2P4M工艺设计与制造,包括前置放大器和偏置电路在内,有源区面积为0.22 mm2。     

一种高灵敏度大动态范围读出电路

为读出光电探测器微弱的响应电流,设计了一种增益自动可调列放大器,提高了读出电路的灵敏度和动态范围,读出电路的动态范围提高了24dB,读出电路功耗为230μW,满足探测器读出要求。读出电路的输出信号可以根据应用要求分别采用线性法和非线性法重建。     

A Low-Voltage Silicon Light Emitting Device in Standard Salicide CMOS Technology

A silicon-based field emission light emitting diode for low-voltage operation is fabricated in the standard 0.35 μm 2P4M salieide complementary metal-oxide-semiconduetor （CMOS） technology. Partially overlapping p^＋ and n^＋ regions with a salicide block layer are employed in this device to constitute a heavily doped p^＋-n^＋ junction which has soft ＂knee＂ Zener breakdown characteristics, thus its working voltage can be reduced preferably below 5 V, and at the same time the power efficiency is improved. The spectra of this device are spread over 500nm to 1000nm with the main peak at about 722nm and an obvious red shift of the spectra peak is observed with the increasing current through the device. During the emission process, field emission rather than avalanche process plays a major role. Differences between low-voltage Zener breakdown emission and high-voltage avalanche breakdown emission performance are observed and compared.     

一种用于UHF波段收发系统的CMOS小数N分频频率综合器

本文设计并实现了一种应用于超高频射频识别（Ultra High Frequency Radio Frequency , UHF）阅读器的ΔΣFractional-N频率综合器。采用4bit的开关电容阵列实现了885MHz~1020M的16 (2^4)个子带的VCO;7/8双模预分频器使用源极电流耦合逻辑（Source Current Mode Logic, SCML）结构的D触发器及脉冲吞吐电路实现;使用四位三阶的Single-loop 结构实现ΔΣ调制器。频率综合器的频率分辨率为200Hz;参考频率为12.95MHz,仿真结果表明当环路带宽为2π×50k时频率锁定时间小于100us。电路采用UMC 0.18μm 2P6M CMOS工艺制备,芯片面积为1.4mm×1.5mm,测试结果表明电源电压1.8V时功耗20mA,测试总输出相位噪声为：-120.6dBc/Hz @1MHz 和 -95.0dBc/Hz @100kHz。     

Low threshold voltage light-emitting diode in silicon-based standard CMOS technology

Low-voltage silicon(Si)-based light-emitting diode(LED) is designed based on the former research of LED in Si-based standard complementary metal oxide semiconductor(CMOS) technology.The low-voltage LED is designed under the research of cross-finger structure LEDs and sophisticated structure enhanced LEDs for high efficiency and stable light source of monolithic chip integration.The device size of low-voltage LED is 45.85×38.4(μm),threshold voltage is 2.2 V in common condition,and temperature is 27 ℃.The external quantum efficiency is about 10-6 at stable operating state of 5 V and 177 mA.     

基于标准CMOS工艺制作的MOS-NDR柔性逻辑电路

本文利用0.35um标准CMOS工艺实现了一种由4个nMOSFET构成的MOS型负阻器件。这种负阻器件的I-V特性与传统的化合物材料构成的共振隧穿二极管（RTD）的特性类似,而且可以通过第三端来调制其I-V特性。基于这种MOS型负阻器件,本文实现了一种通过调节阈值电压来实现与非门（NAND）到或非门（NOR）转变的柔性逻辑电路。此种电路所用器件较少,而且由于使用标准IC的设计和工艺流程,制作工艺大大简化。     

Silicon Light Emitting Devices in CMOS Technology

Two silicon light emitting devices with different structures are realized in standard 0.35pro complementary metal-oxide-semiconductor （CMOS） technology. They operate in reverse breakdown mode and can be turned on at 8.3 V. Output optical powers of 13.6nW and 12.1 n W are measured at 10 V and l OOmA, respectively~ and both the calculated light emission intensities are more than 1 mW/cm^2. The optical spectra of the two devices are between 600-790 nm with a clear peak near 760 nm.