应用于高速CMOS图像传感器的10比特列并行循环式ADC

This paper presents a high-speed column-parallel cyclic analog-to-digital converter(ADC) for a CMOS image sensor.A correlated double sampling(CDS) circuit is integrated in the ADC,which avoids a stand-alone CDS circuit block.An offset cancellation technique is also introduced,which reduces the column fixed-pattern noise(FPN) effectively.One single channel ADC with an area less than 0.02 mm~2 was implemented in a 0.13μm CMOS image sensor process.The resolution of the proposed ADC is 10-bit,and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively.The power consumption from 3.3 V supply is only 0.66 mW.An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels.The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.     

新型城镇化背景下工业型城镇空间规划引导初探——以慈溪市观海卫镇为例

推进新型城镇化是新时期的重要战略任务,是各城镇走向健康、可持续发展的主要路径之一.为此,以慈溪市观海卫镇为例,通过实地调研和问题思考,分析工业型城镇的空间发展历程及特征,指出其存在以外延扩张式发展为主导、开发模式亟待转变、用地布局杂乱、缺乏有序引导、公建设施与公共空间不足等问题.新型城镇化战略下,工业型城镇应加快城镇产业转型和城乡产业协同发展,促进城镇发展动力多元化;转变城镇发展模式,注重城镇内涵式发展;以人为本,提高城镇品质,建设现代化城镇.     

Observation of lateral long range order in superconducting FeTe thin films

<正>We find that the superconductivity in the thin films of the formerly believed non-superconducting parent compound FeTe is accompanied by an emergence of second order with a correlation length of 742 nm and 258 nm at 10 K and 300 K,respectively.The structural phase transition found in iron pnictide superconductors,in non-superconducting FeTe bulk samples,and in FeSe superconducting thin films is not observed in the superconducting FeTe thin films.The interplay between superconductivity and long range order may suggest the crucial role of competition between electronic localization and itinerancy which leads to strong quantum fluctuations in the FeTe system.     

用于降低高速CMOS图像传感器电荷转移时间的工艺技术

This paper proposes pixel process techniques to reduce the charge transfer time in high speed CMOS image sensors.These techniques increase the lateral conductivity of the photo-generated carriers in a pinned photodiode(PPD) and the voltage difference between the PPD and the floating diffusion(FD) node by controlling and optimizing the N doping concentration in the PPD and the threshold voltage of the reset transistor,respectively.The techniques shorten the charge transfer time from the PPD diode to the FD node effectively.The proposed process techniques do not need extra masks and do not cause harm to the fill factor.A sub array of 3264 pixels was designed and implemented in the 0.18 m CIS process with five implantation conditions splitting the N region in the PPD.The simulation and measured results demonstrate that the charge transfer time can be decreased by using the proposed techniques.Comparing the charge transfer time of the pixel with the different implantation conditions of the N region,the charge transfer time of 0.32 s is achieved and 31% of image lag was reduced by using the proposed process techniques.     

FeSe_(0.4)Te_(0.6)超导薄膜的输运性质实验研究

通过脉冲激光沉积技术制备了超导转变温度约为12 K的FeSe0.4Te0.6超导薄膜,测量了该薄膜晶体结构和在磁场(0-12 T)下的电输运性质。分别用传统的Arrhenius Plots和一种更精确的关系对薄膜的TAFF区的热激活能进行了分析,得到激活能对磁场和温度的指数关系;对两种方法分析结果分析比较,发现第二种方法的分析结果更符合FeSe0.4Te0.6超导薄膜的测量结果。估算了FeSe0.4Te0.6超导薄膜的玻璃态转变温度、上临界场Hc2(0)和相干长度。     

应用于高速CMOS图像传感器的具有动态功耗控制的12比特紧凑型列并行逐次逼近ADC

本文提出了一个应用于高速CMOS图像传感器的12比特列并行逐次逼近模数转换器。为了减小面积并使它的版图与两倍的像素间距相适应,采用了分段二进制权重开关电容数模转化器和交错结构的金属-氧化物-金属单位电容。为了消除单位电容上极板的寄生电容,提出了电场屏蔽的版图结构画法。提出了动态功耗控制技术,有效地降低了读出通道的功耗。用片外前台数字校准算法补偿开关电容数模转化器电容失配引起的非线性。芯片采用1P5M CMOS图像传感器工艺制造,其面积为20×2020μm2。采样率为833kS/s时,校准后的DNL、INL、ENOB分别为：0.9/-1 LSB、1/-1.1LSB、11.24比特。在1.8V的电源电压下,功耗为0.26 mW。随着帧率的减小,功耗线性减少。