Testing content addressable memories with physical fault models

Content addressable memory （CAM） is widely used and its tests mostly use functional fault models. However, functional fault models cannot describe some physical faults exactly. This paper introduces physical fault models for write-only CAM. Two test algorithms which can cover 100% targeted physical faults are also proposed. The algorithm for a CAM module with N-bit match output signal needs only 2N＋2L＋4 comparison operations and 5N writing operations, where N is the number of words and L is the word length. The algorithm for a HIT-signal-only CAM module uses 2N＋2L＋5 comparison operations and 8N writing operations. Compared to previous work, the proposed algorithms can test more physical faults with a few more operations. An experiment on a test chip shows the effectiveness and efficiency of the proposed physical fault models and algorithms.     

一种 65纳米 CMOS 10–20 Gb/s PAM2-4接收和发送端

本文提出了65纳米CMOS工艺下的一种 10Gb/s PAM2, 20Gb/s PAM4高速低功耗的有线电互连发送和接收端。发送端面积为430μm × 240μm,功耗为 50.56mW。通过集成可编程的 5阶预加重均衡器,发送端可以在宽范围区间内补偿各种不同的信道损失,并且针对信道特点的不同采用相应的发送电压幅度从而降低信号发送功耗。接收端均衡器面积为146μm × 186μm,功耗为5.3mW。     

一个低功耗高摆幅电压模式发送端

本文设计完成了一个28纳米工艺下的低功耗电压模式发送端. 相比于电流模式发送端。电压模式发送端输出更大摆幅的信号的同时功耗更低。发送端通过电压转换器被分为两个电压域用于减小功耗。另外,本文提出的电压结构能够实现相互独立的阻抗匹配和均衡控制。 芯片实测发送端可输出差分摆幅880毫伏的信号,并且每个通道的功耗仅为23毫瓦。     

A 10-20 Gb/s PAM2-4 transceiver in 65 nm CMOS

This paper presents the design of a 10 Gb/s PAM2, 20 Gb/s PAM4 high speed low power wire-line transceiver equalizer in a 65 nm CMOS process with 1 V supply voltage. The transmitter occupies 430 × 240 μm2 and consumes 50.56 mW power. With the programmable 5-order pre-emphasis equalizer, the transmitter can compensate for a wide range of channel loss and send a signal with adjustable voltage swing. The receiver equalizer occupies 146 × 186μm^2 and consumes 5.3 mW power.