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Based on the devised system-level design methodology,a 2.5-Gb/s monolithic bang-bang phase-locked clock and data recovery(CDR) circuit has been designed and fabricated in SMIC's 0.18-μm CMOS technology.The Pottb(a|¨)cker phase frequency detector and a differential 4-stage inductorless ring VCO are adopted,where an additional current source is added to the VCO cell to improve the linearity of the VCO characteristic.The CDR has an active area of 340×440μm~2,and consumes a power of only about 60 mW from a 1... 相似文献
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针对粘弹塑性统一本构模型参效众多的特点和传统评估参效方法的缺点,应用非线性最小二秉法与敏感系数分析方法相结合,提出了一个比较系统的对粘弹塑性统一本构模型的参数进行评估的方法。对铜合金在室温下不同加载速率的试验曲线进行参数适配,表明本方法的合理性与正确性。为粘弹塑性统一本构模型的工程应用奠定了基础。 相似文献
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A lateral double-diffused metal-oxide-semiconductor field effect transistor (LDMOST) with multiple n-regions in the p-substrate is investigated in detail. Because of the decrescent n-regions, the electric field distribu- tion is higher and more uniform, and the breakdown voltage of the new structure is increased by 95%, in comparison with that of a conventional counterpart without substrate n-regions. Based on the trade-off between the breakdown voltage and the on-resistance, the optimal number of n-regions and the other key parameters are achieved. Furthermore, sensitivity research shows that the breakdown voltage is relatively sensitive to the drift region doping and the n-regions' lengths. 相似文献
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高速时钟与数据恢复电路技术研究 总被引:1,自引:0,他引:1
本文根据数据恢复时,本地时钟与输入数据之间的相位关系及其实现方式的不同,将高速时钟与数据恢复(CDR,Clock and Data Recovery)电路技术分为三类,也即前馈相位跟踪型,反馈相位跟踪型,以及盲过采样型。进而又分别对每一类型进行了细分并分别进行了深入的剖析和比较。最后又给出了不同应用环境下,CDR技术的选择策略,并指出了CDR技术的发展趋势。本文通过对高速CDR技术详尽而又深刻的分析比较,勾勒出了一个高速CDR技术的关系及发展演化图,使读者能够对现存的高速CDR技术及其发展趋势有一个前面而又清晰的认识。 相似文献
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针对统计量算法盲检测QAM信号的缺陷,该文提出了一个实虚型连续多值复数Hopfield神经网络算法,该网络的实部、虚部各含一个连续多值实激活函数.该文构造了适用于该网络的能量函数,并分别在异步和同步更新模式下证明了该神经网的稳定性.当该神经网的权矩阵借助接收数据补投影算子构成时,该实虚型连续多值复数Hopfield神经网络可有效地实现QAM信号盲检测.仿真试验表明:该算法采用较短接收数据即可到达全局真解点,并且适用于含公零点信道. 相似文献
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采用SMIC 0.18-μm CMOS 工艺设计并实现了一款基于锁相原理的单片Bang-Bang时钟恢复电路。从系统级及电路级详细论述了本电路的设计方法。本电路的有效面积为340×440 μm2。在1.8V电压下的功耗仅仅为60mW,输入灵敏度不到25mV,输出单端摆幅超过300mV。它具有800MHz的牵引带宽,相位噪声为 -111.54 dBc/Hz @10 kHz。本电路可以可靠地工作在1.8 Gb/s 到2.6 Gb/s之间的任意数据输入速率,而不需要任何参考时钟,外部调谐或外接元件。 相似文献
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An analytical model for nanowire junctionless SOI Fin FETs with considering three-dimensional coupling effect 下载免费PDF全文
In this paper, the three-dimensional(3D) coupling effect is discussed for nanowire junctionless silicon-on-insulator(SOI) Fin FETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional(2D) potential model is proposed for the subthreshold region of junctionless SOI Fin FET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted. 相似文献