Multi-bits error detection and fast recovery in RISC cores

The particles-induced soft errors are a major threat to the reliability of microprocessors. Even worse, multi-bits upsets (MBUs) are ever-increased due to the rapidly shrinking feature size of the IC on a chip. Several architecture-level mechanisms have been proposed to protect microprocessors from soft errors, such as dual and triple modular redundancies (DMR and TMR). However, most of them are inefficient to combat the growing multi-bits errors or cannot well balance the critical paths delay, area and power penalty. This paper proposes a novel architecture, self-recovery dual-pipeline (SRDP), to effectively provide soft error detection and recovery with low cost for general RISC structures. We focus on the following three aspects. First, an advanced DMR pipeline is devised to detect soft error, especially MBU. Second, SEU/MBU errors can be located by enhancing self-checking logic into pipelines stage registers. Third, a recovery scheme is proposed with a recovery cost of 1 or 5 clock cycles. Our evaluation of a prototype implementation exhibits that the SRDP can successfully detect particle-induced soft errors up to 100% and recovery is nearly 95%, the other 5% will inter a specific trap.     

一种基于分段并行思想的PCB布线加速策略

基于网格的搜索布线方式是印制电路板PCB自动布线的主要手段.随着电路系统的规模不断增大、功能日益复杂,PCB布线设计的挑战也不断增大.针对PCB布线地图规模较大且元器件障碍物较多的布线场景,常用的Lees和A~*等布线算法突显出着搜索空间迅速增大且无法有效解决多网络布线顺序的问题.由此,提出一种基于分段并行思想的布线加速策略以提升布线效率.其基本思路为：将一个较大区域内的搜索问题分解成多个小区域内的并行搜索问题,并且针对不同区域内障碍物的特征采用自适应的启发引导函数,从而实现有效减少搜索空间、加快搜索速度、优化布线效果.模拟实验表明,在150×150的网格布线场景中,所提方法与Lees算法和A~*算法相比较,搜索速度分别可提升160倍和17倍.     

自由大气紫外光通信中几类光源的比较和研究

介绍了几类应用于自由大气紫外光通信系统的紫外日盲区光源,并对其谱线分布、驱动方式、发射功率、转换效率等特点进行了比较分析,以期为紫外光通信系统的设计提供参考.     

一种D类推挽放大电路的设计

提出一种基于CPLD的D类功率放大电路的设计,该设计改进了传统C类功率放大电路效率低、对管不易匹配、调试不方便等不足之处,同时采用EPM240T100CS CPLD作为放大电路的控制与保护单元,其工作效率更高,性能更稳定、可靠。还给出了CPLD中的电路模块框图和Verilog设计流程图。该设计中的D类推挽放大电路主要应用于调幅与调频通用的功率发射机的研制,以期为相似设计提供参考。     

基于周期粒度的级间寄存器备份机制

单粒子翻转是空间环境下微处理器发生异常的重要诱因之一,随着集成电路特征尺寸的缩小,单粒子翻转不仅会引发单位错误,还会引发大量的多位错误,如何有效解决处理器所面临的多位故障是容错处理器设计面临的新挑战.本文提出了一种基于周期粒度的级间寄存器备份机制的容错方法,采用双流水线冗余结构,通过比较器对比两条流水线的级间寄存器以检测单粒子故障;以周期粒度对级间寄存器的内容进行备份,当检测到单粒子故障时,使用2个周期对流水线进行恢复;为避免脏数据流出流水线,在数据缓存和寄存器堆的入口设置写缓冲,通过延迟写入保证信息可靠性.本文基于实际的SPARC V8结构处理器,对提出的方法进行了具体实现,在实验平台上进行了仿真,仿真结果显示,本文提出的容错方法能够以一定的面积开销实现对SEU、SET、和MBU故障容错,加固处理器的主频最高可以提升70%.     

专用语音处理芯片AC48105在低速语音编码设备中的应用

AC48105是以色列AudioCodes公司生产的一种专用语音处理芯片，可用于完成低比特率的语音压缩编码解压和传真等功能.该芯片内含5路相互独立的复用信道，可以传输语音、传真和数据信息，带有的16位DSP内核可提供多种语音编码格式。文中结合该芯片在低速语音编码设备中的应用，详细介绍了其工作模式及配置方法。     

紫外光通信在军事通信系统中的应用

介绍了紫外光通信的性能特点、链路工作方式及影响紫外光通信的主要因素,并分析了紫外光音频通信系统的设备构成及其在军事作战和演习中的应用。     

Multi-bit upset aware hybrid error-correction for cache in embedded processors

For the processor working in the radiation environment in space, it tends to suffer from the single event effect on circuits and system failures, due to cosmic rays and high energy particle radiation. Therefore, the reliability of the processor has become an increasingly serious issue. The BCH-based error correction code can correct multi-bit errors, but it introduces large latency overhead. This paper proposes a hybrid error correction approach that combines BCH and EDAC to correct both multi-bit and single-bit errors for caches with low cost. The proposed technique can correct up to four-bit error, and correct single-bit error in one cycle. Evaluation results show that, the proposed hybrid error-correction scheme can improve the performance of cache accesses up to 20% compared to the pure BCH scheme.