超薄Ni0.86Pt0.14金属硅化物薄膜特性

通过研究超薄Ni0.86Pt0.14金属硅化物薄膜的特性,提出采用310℃/60 s与480℃/10 s两步快速热退火(RTA)的工艺方案,形成的Ni(Pt)硅化物薄膜电阻率最小,均匀性最好,且在600℃依然保持形态稳定。应用此退火条件,Ni0.86Pt0.14在0.5μm和22 nm CMOS结构片中形成覆盖均匀且性能良好的金属硅化物薄膜,同时没有形成任何尖峰。对于更薄的硅化物,实验结果表明,2 nm Ni0.86Pt0.14形成的超薄硅化物界面平整,均匀性好,没有在界面出现Ni0.95Pt0.05金属硅化物的"倒金字塔形"尖峰。结果显示,比较在有、无氩离子轰击的硅表面形成的两种Ni(Pt)Si硅化物薄膜,后者比前者电阻率约低10%~26%,该工艺有望在未来超薄硅化物制作被广泛应用。     

关于超薄埋氧层及超薄SOI的MOSFET器件衬底掺杂的设计研究

The importance of substrate doping engineering for extremely thin SOI MOSFETs with ultra-thin buried oxide(ES-UB-MOSFETs) is demonstrated by simulation.A new substrate/backgate doping engineering,lateral non-uniform dopant distributions(LNDD) is investigated in ES-UB-MOSFETs.The effects of LNDD on device performance,V t-roll-off,channel mobility and random dopant fluctuation(RDF) are studied and optimized.Fixing the long channel threshold voltage(V t) at 0.3 V,ES-UB-MOSFETs with lateral uniform doping in the substrate and forward back bias can scale only to 35 nm,meanwhile LNDD enables ES-UB-MOSFETs to scale to a 20 nm gate length,which is 43% smaller.The LNDD degradation is 10% of the carrier mobility both for n MOS and p MOS,but it is canceled out by a good short channel effect controlled by the LNDD.Fixing V t at 0.3 V,in long channel devices,due to more channel doping concentration for the LNDD technique,the RDF in LNDD controlled ES-UB-MOSFETs is worse than in back-bias controlled ES-UB-MOSFETs,but in the short channel,the RDF for LNDD controlled ES-UB-MOSFET is better due to its self-adaption of substrate doping engineering by using a fixed thickness inner-spacer.A novel process flow to form LNDD is proposed and simulated.     

可垂直集成的无电容式动态存储器件

A two-port capacitorless PNPN device with high density,high speed and low power memory fabricated using standard CMOS technology is presented.Experiments and calibrated simulations were conducted which prove that this new memory cell has a high operation speed(ns level),large read current margin(read current ratio of 10~4×),low process variation,good thermal reliability and available retention time(190 ms).Furthermore,the new memory cell is free of the cyclic endurance/reliability problems induced by hot-carrier injection due to the gateless structure.     

场效应晶体管中接触孔应力技术的研究

随着集成电路集成度的不断提高以及场效应晶体管尺寸的微缩,沟道载流子迁移率退化越来越严重,通过沟道应力技术提升载流子迁移率从而提高性能的技术被广泛应用。介绍了接触孔应力对沟道的影响,分析了接触孔与沟道间距离及源漏区外延厚度对沟道应力的影响。通过对应力传导机制的分析,提出了通过调节侧墙材料和结构来优化沟道应力的方法。     

注入与原位掺杂ETSOI PMOSFETs性能模拟分析

利用TCAD对注入掺杂和原位掺杂ETSOI PMOSFETs进行模拟仿真分析。用从模拟中提取出来的关键特性参数进行对比,以此分析它们性能优劣。在Vtsat一样时,25 nm 栅长注入掺杂器件Ion比原位掺杂的要大200 uA/um左右。同时,9~11 nm Tsi注入掺杂器件的DIBL和SSsat也要小30~50 mV/V 和 6.3~9.1 mV/dec。在栅长为15 nm时,原位掺杂器件的ΔVtsat为-31.8 mV/nm,而注入掺杂器件却仅有-6.8 mV/nm。这些仿真结果表明通过注入得到的ETSOI PMOSFET器件性能比原位掺杂的性能更好,更稳定。     

碳注入对 Ni0.95(Pt0.05)Si热稳定性影响探究

在两步快速热退火硅化之前,对硅衬底进行不同剂量的碳注入,以此探究碳对Ni0.95(Pt0.05)Si薄膜热稳定性的影响。与没有碳注入的比起来,1e15 cm-2和3e15 cm-2碳剂量注入得到的Ni0.95(Pt0.05)Si薄膜热稳定性分别被改善了100 oC和150 oC。通过方块电阻测量,XRD物相分析和SEM图像对比发现,沉淀在Ni0.95(Pt0.05)Si晶界处和Ni0.95(Pt0.05)Si/Si的界面处的碳原子是Ni0.95(Pt0.05)Si薄膜热稳定性提高的原因,而且碳的注入还在一定程度上改变了硅化反应中NiSi晶粒生长的择优取向。这些发现对Ni0.95(Pt0.05)Si:C材料的应用都将很有意义。