一种基于XILINX ISE的可重配置滤波器设计

文章详细介绍了一种基于XILINX ISE开发环境下的可重构滤波器设计,可重构滤波器具有系数实时可变,通阻带实时可配的特征,在实际工程环境下有广泛的应用需求。     

基于XILINX ISE平台的宽带接收机系统设计

将介绍基于XILINX ISE平台下的高速多路并行宽带接收机系统设计。涵盖前端AD采集卡的选择,基于XILINX FPGA的多路并行信号处理流程设计,并提供ISE集成开发环境下的仿真设计流程及仿真结果分析。整体系统流程设计充分考虑系统资源配置,最优化系统设计,设计结果具有较高的工程的参考意义。     

引入籽晶层的物理溅射生长Ga2O3外延薄膜特性研究

氧化镓(Ga₂O₃)薄膜在功率器件以及紫外探测等领域中具有重要的应用潜力,而实现高质量薄膜制备则是其中的关键.本文在蓝宝石衬底上物理溅射生长外延Ga₂O₃层,因采用引入籽晶层的方法提供了人为成核点而使得外延层结晶质量获得明显改善.实验发现该外延层薄膜的生长中随着功率增加,晶粒团聚到一定尺寸后出现裂解现象.这一物理机制归因于大功率下溅射粒子在生长晶面上扩散携带的能量过大导致粒子碰撞次数增多.文中生长的外延层为(201)晶面取向的β型Ga₂O₃薄膜,厚度在202.4-292.3 nm之间,薄膜在450—800 nm范围可见光波段的透射率约为90%,吸收边随着功率的增加先蓝移后红移,带隙约为4.81—4.96 eV.光致发光光谱分析表明,该外延层薄膜在460 nm处产生蓝色发光.本文发现溅射功率为160 W时引入籽晶层生长的β-Ga₂O₃薄膜具有最佳的结晶质量,这一方法将为高质量β-Ga₂O     

基于覆盖率驱动的双模导航芯片验证平台构建

本文介绍了一种基于覆盖率驱动的双模导航芯片验证系统,该系统基于典型的UVM方法学结构,具有自动激励产生、自动结果比较及自动覆盖率收集等功能。本文应用该系统对双模导行芯片进行了完备性验证,达到了功能覆盖率100%的总体目标。     

基于System Generator的信道化发射模块设计

介绍了一种基于System Generator的数字信道化模块设计方法。系统介绍了发射信道化的基本原理和两种常用的发射信道化模块结构,以及基于System Generator辅助设计下的硬件设计流程。设计中充分考虑了XILINX IP核的应用,设计结果具有一定的参考价值。     

Temperature-Dependent Effect of Near-Interface Traps on SiC MOS Capacitance

A two-dimensional electrical SiC MOS interface model including interface and near-interface traps is established based on the relevant tunneling and interface Shockley–Read–Hall model. The consistency between simulation results and measured data in the different temperatures shows that this interface model can accurately describe the capture and emission performance for near-interface oxide traps, and can well explain the hysteresis-voltage response with increasing temperature, which is intensified by the interaction between deep oxide traps and shallow oxide traps. This also indicates that the near-interface traps result in an increase of threshold-voltage shift in SiC MOSFET with increasing temperature.     

基于System Generator的信道化发射模块设计

介绍了一种基于SystemGenerator的数字信道化模块设计方法。系统介绍了发射信道化的基本原理和两种常用的发射信道化模块结构,以及基于System Generator辅助设计下的硬件设计流程。设计中充分考虑了XILINX IP核的应用,设计结果具有一定的参考价值。     

Effect of NO annealing on charge traps in oxide insulator and transition layer for 4H-SiC metal–oxide–semiconductor devices

The effect of nitric oxide(NO) annealing on charge traps in the oxide insulator and transition layer in n-type4H–Si C metal–oxide–semiconductor(MOS) devices has been investigated using the time-dependent bias stress(TDBS),capacitance–voltage(C–V),and secondary ion mass spectroscopy(SIMS).It is revealed that two main categories of charge traps,near interface oxide traps(Nniot) and oxide traps(Not),have different responses to the TDBS and C–V characteristics in NO-annealed and Ar-annealed samples.The Nniotare mainly responsible for the hysteresis occurring in the bidirectional C–V characteristics,which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor.However,Not is mainly responsible for the TDBS induced C–V shifts.Electrons tunneling into the Not are hardly released quickly when suffering TDBS,resulting in the problem of the threshold voltage stability.Compared with the Ar-annealed sample,Nniotcan be significantly suppressed by the NO annealing,but there is little improvement of Not.SIMS results demonstrate that the Nniotare distributed within the transition layer,which correlated with the existence of the excess silicon.During the NO annealing process,the excess Si atoms incorporate into nitrogen in the transition layer,allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of Nniot.     

一种基于XILINXIP核的并行架构内插滤波器实现

文章详细介绍了一种可应用于高速信号处理中的并行内插滤波器设计,涵盖了低通及带通内插滤波器的设计原理、多路并行滤波器设计方法以及基于XILINX FIR IP核的设计实现,在高速数据信号处理领域有一定的借鉴价值。