基于SoC可配置CF/CF+卡控制器的设计

基于最新的CF/CF 3.0协议,设计了一款基于AHB总线的可配置的CF/CF 卡控制器.设计采用了高性能乒乓操作方式的改进异步FIFO.针对CF/CF 卡实际使用时往往只需要其某一两种模式的特点,采用了一种可定制可裁剪CF/CF 控制器电路的设计思路,极大地提高设计效率;探讨了一种基于SoC高性能接口控制器电路通用体系架构,已成功应用到多种接口控制器的设计中.设计通过了仿真(NC-Verilog)、综合(DC)以及FPGA验证,嵌入到单板系统中,实现了与CF存储卡之间的数据传输.     

F注入AlGaN/GaN增强型HEMT

The fabrication of enhancement-mode AlGaN/GaN HEMTs by fluorine plasma treatment on sapphire substrates is reported. A new method is used to fabricate devices with different fluorine plasma RF power treatments on one wafer to avoid differences between different wafers. The plasma-treated gate regions of devices treated with different fluorine plasma RF powers were separately opened by a step-and-repeat system. The properties of these devices are compared and analyzed. The devices with 150 W fluorine plasma treatment power and with 0.6 μm gate-length exhibited a threshold voltage of 0.57 V, a maximum drain current of 501 mA/mm, a maximum transconductance of 210 mS/mm, a current gain cutoff frequency of 19.4 GHz and a maximum oscillation frequency of 26 GHz. An excessive fluorine plasma treatment power of 250 W results in a small maximum drain current, which can be attributed to the implantation of fluorine plasma in the channel.     

基于扇形模板的数字集成电路规律性提取算法

 将数据挖掘方法用于数字集成电路规律性提取,提出了一种扇形结构模板的规律性提取算法.采用压缩式存储及删除缓冲器结构等方法,降低了电路的存储空间.通过边权值编码,实现了逐级产生扇形频繁子电路的算法,解决了传统算法对大规模数字集成电路规律性提取时间复杂度过高的问题.实验结果表明该算法比SPOG与TREE算法更能充分提取电路的规律性,规律性提取时间更短.     

Monolithically integrated enhancement/depletion-mode AlGaN/GaN HEMT D flip-flop using fluorine plasma treatment

Depletion-mode and enhancement-mode AlGaN/GaN HEMTs using fluorine plasma treatment were integrated on one wafer.Direct-coupled FET logic circuits,such as an E/D HEMT inverter,NAND gate and D flip-flop,were fabricated on an AlGaN/GaN heterostructure.The D flip-flop and NAND gate are demonstrated in a GaN system for the first time.The dual-gate AlGaN/GaN E-HEMT substitutes two single-gate E-HEMTs for simplifying the NAND gate and shrinking the area,integrating with a conventional AlGaN/GaN D-HEMT and demonstrating a NAND gate.E/D-mode D flip-flop was fabricated by integrating the inverters and the NAND gate on the AlGaN/GaN heterostructure.At a supply voltage of 2 V,the E/D inverter shows an output logic swing of 1.7 V,a logic-low noise margin of 0.49 V and a logic-high noise margin of 0.83 V.The NAND gate and D flip-flop showed correct logic function demonstrating promising potential for GaN-based digital ICs.     

一种数字集成电路链状频繁子电路提取算法

基于数据挖掘思想,提出一种链状结构模板的规律性提取算法,解决集成电路规律性提取算法复杂度过高的问题.通过对边权值进行编码,将复杂子电路的同构搜索转化为边权值序列的匹配问题.模板扩展过程利用剪枝策略删除非频繁子电路,提高了规律性提取效率.将模板的产生与子电路的同构搜索过程合并,简化规律性提取流程.解决大规模集成电路中规则性提取复杂度过高的问题.结果表明,算法比SPOG与TREE算法更能充分提取电路的规律性,得到较好的电路覆盖.     

AlGaN/GaN double-channel HEMT

正The fabrication of AlGaN/GaN double-channel high electron mobility transistors on sapphire substrates is reported.Two carrier channels are formed in an AlGaN/GaN/AlGaN/GaN multilayer structure.The DC performance of the resulting double-channel HEMT shows a wider high transconductance region compared with single-channel HEMT. Simulations provide an explanation for the influence of the double-channel on the high transconductance region.The buffer trap is suggested to be related to the wide region of high transconductance.The RF characteristics are also studied.     

基于SoC低功耗MMC卡控制器的设计

本文基于最新的MMC4.1协议,设计了一款基于AHB总线的低功耗MMC卡控制器.设计采用了高性能改进异步FIFO.针对MMC卡常用于便携式产品中的低功耗需求,采用了动态功耗管理和门控时钟技术,可降低功耗约60%;探讨了一种基于SoC高性能接口控制器电路通用体系架构,已成功应用到多种接口控制器的设计中.设计通过了仿真(NC-Verilog)、综合(DC)以及FPGA验证,嵌入到单板系统中,实现了与MMC存储卡之间的数据传输.     

一种新的加法器进位旁路电路

,从逻辑关系上优化了进位旁路加法器中的进位旁路电路,并采用差分串联电压开关传输门(DCVSPG)逻辑电路实现.该方法解决了传统静态曼彻斯特链进位旁路电路的逻辑冲突问题,又避免了动态曼彻斯特链进位旁路电路在预充阶段的延迟和功耗开销.DCVSPG逻辑进位旁路比静态曼彻斯特链进位旁路和动态曼彻斯特链进位旁路分别节省了25%和...     

F等离子体处理增强型及耗尽型AlGaN/GaN HEMT集成的D触发器

耗尽型和F等离子体处理增强型高电子迁移率晶体管（HEMT）被集成在同一圆片上。增强型/耗尽型 HEMT反向器、与非门以及D触发器等直接耦合场效应晶体管逻辑电路被制作在AlGaN/GaN异质结上。D触发器在GaN体系中首次被实现。在电源电压为2伏的条件下,增强型/耗尽型反向器显示输出逻辑摆幅为1.7伏,逻辑低噪声容限为0.49伏,逻辑高噪声容限为0.83伏。与非门和D触发器的功能正确,证实了GaN基数字电路的发展潜力。