内嵌SCR的LDMOS器件双骤回ESD特性研究

基于寄生参数分析,对内嵌SCR的LDMOS器件给出了二次骤回发生判据。本文对三种典型结构进行了数值仿真和比较,并基于此判据仿真优化了影响二次骤回的器件结构参数,从而提高器件ESD性能。TLP试验数据表明,当二次骤回电压由25.4V降低到8.1V时,器件ESD泄放能力由0.57A提高到3.1A。     

ESD应力下LDMOS器件软失效的分析及优化

分析了发生软失效的两种原因:电场诱导和热诱导。针对一种采用0.35μm BCD工艺的LDMOS器件,讨论了改变器件漂移区长度对软泄漏电流的影响。最终通过对漂移区长度以及源端和衬底接触间距的优化,消除了器件原先存在的软泄漏电流现象,并且没有过分增大器件的触发电压。     

ESD robustness studies on the double snapback characteristics of an LDMOS with an embedded SCR

Criterion for the second snapback of an LDMOS with an embedded SCR is given based on parasitic parameter analysis.According to this criterion,three typical structures are compared by numerical simulation and structural parameters which influence the second snapback are also analyzed to optimize the ESD characteristics. Experimental data showed that,as the second snapback voltage decreased from 25.4 to 8.1 V,the discharge ability of the optimized structure increased from 0.57 to 3.1 A.     

A novel enhancement mode AlGaN/GaN high electron mobility transistor with split floating gates

A novel enhancement-mode AlGaN/GaN high electron mobility transistor(HEMT) is proposed and studied.Specifically,several split floating gates(FGs) with negative charges are inserted to the conventional MIS structure.The simulation results revealed that the V_(th) decreases with the increase of polarization sheet charge density and the tunnel dielectric(between FGs and AlGaN) thickness,while it increases with the increase of FGs sheet charge density and blocking dielectric(between FGs and control gate) thickness.In the case of the same gate length,the V_(th) will left shift with decreasing FG length.More interestingly,the split FGs could significantly reduce the device failure probability in comparison with the single large area FG structure.     

LDMOS器件源-衬版图结构优化对ESD性能影响的研究

To enhance the robustness of LDMOS ESD protection devices, the influence of a source-bulk layout structure is analyzed by theoretical analysis and numerical simulation. Novel structures with varied source-bulk layout structures are fabricated and compared. As demonstrated by TLP testing, the optimized structure has an 88% larger It2 than a conventional one, and its Vtl is reduced from 55.53 to 50.69 V.     

5V CMOS中GGNMOS ESD失效电流和沟道长度正向关系的分析

Contrary to general understanding,a test result shows that devices with a shorter channel length have a degraded ESD performance in the advanced silicided CMOS process.Such a phenomenon in a gate-grounded NMOSFET(GGNMOS) was investigated,and the current spreading effect was verified as the predominant factor. Due to transmission line pulse(TLP) measurements and Sentaurus technology computer aided design(TCAD) 2-D numerical simulations,parameters such as current gain,on-resistance and power density were discussed in detail.     

一种用于高压应用的700V BCD工艺平台

针对高压应用领域,建立了一种700V的高压 BCD兼容工艺平台。采用全注入技术在p型单晶衬底上,仅用10张光刻版即实现了700V nLDMOS、200V nLDMOS、80V nLDMOS、60V nLDMOS、40V nLDMOS、700V nJFET和低压器件的单片集成。工艺中没有采用外延层或埋层,极大地节约了制造成本。其中,高压双RESURF LDMOS的击穿电压为800V,比导通电阻为206.2 mohm.cm₂。该700V 高压 BCD兼容工艺平台具有低成本、工艺简单的优势,可使得功率集成电路产品具有较小的芯片面积。     

衬底寄生电阻对高压器件ESD性能的影响

随着高压集成电路的广泛应用,高压器件的ESD性能越来越受广大设计者的重视。从理论上分析了衬底寄生电阻对高压LDMOS器件ESD特性的影响,采用几种结构,对上述参数进行优化,并在0.35μm BCD工艺下进行流片试验。测试结果表明,优化衬底电阻可以有效地提高器件的ESD泄放能力,最优结构的二次击穿电流由原始器件的0.75A增大到3.3A。     

寄生电阻对高压器件ESD性能的影响

本文从理论上分析了衬底寄生电阻以及漏端镇流电阻对高压LDMOS器件ESD特性的影响。文中采用了多种结构对上述参数进行优化,并将其在0.35μm BCD工艺下进行试验,测试结果表明增加寄生电阻可以有效地提高器件的ESD泄放能力,最优结构的二次击穿电流由原始器件的0.75A增大到3.5A,即泄放电流增加了367%。