一款应用于多通道CZT探测器的12-bit 1MS/s SAR-ADC芯片

本文提出了一种应用于多通道CZT探测器低功耗、小面积、抗辐照12位1MS/s逐次逼近模数转换器芯片。为了提高SAR-ADC的精度,提出了一种新型比较器,该比较器能够实现失调电压自校准功能。同时为了减少电荷分配DAC中电容失配的问题,提出了分散式电容阵列。通过电路级和版图级技术加固,提高该SAR-ADC芯片的抗辐照能力。原型芯片采用TSMC 0.35um 2P4M CMOS工艺。电源电压为3.3V和5V,采样率是1MS/s。该SAR-ADC芯片能够实现高达67.64dB的信纳比SINAD,然而仅消耗10mWz功耗。该芯片核心面积为1180um×1080um。     

基于ANSYS有限元分析法的LED结温检测北大核心CSCD

发光二极管(LED)作为第四代照明光源,其发光性能不但和电学特性相关,还受pn结结温的影响。LED的发光效率随着结温的升高而降低,LED的使用寿命也会随之减小。因此对LED结温进行准确检测具有重要的意义。利用Fluke Ti20红外测温摄像仪和ANSYS有限元软件模拟仿真结合的方法来分析LED模块的结温,并与标准电压法测得的结温进行对比。利用该方法获得的仿真结果与电压法实测LED结温值误差小于2%,与红外测温仪实测结果相差不超过5%。实验证实该方法可以作为LED非接触式结温分析的一种有效的工程方法。     

应用于碲锌镉探测器逐次逼近模数转换器基准电压的研究

An on-chip reference voltage has been designed in capacitor-resister hybrid SAR ADC for CZT detector with the TSMC 0.35 μ m 2P4M CMOS process. The voltage reference has a dynamic load since using variable capacitors and resistances, which need a large driving ability to deal with the current related to the time and sampling rate. Most of the previous articles about the reference for ADC present only the bandgap part for a low temperature coefficient and high PSRR. However, it is not enough and overall, it needs to consider the output driving ability. The proposed voltage reference is realized by the band-gap reference, voltage generator and output buffer. Apart from a low temperature coefficient and high PSRR, it has the features of a large driving ability and low power consumption. What is more, for CZT detectors application in space, a radiation-hardened design has been considered. The measurement results show that the output reference voltage of the buffer is 4.096 V. When the temperature varied from 0 to 80℃, the temperature coefficient is 12.2 ppm/℃. The PSRR was-70 dB@100 kHz. The drive current of the reference can reach up to 10 mA. The area of the voltage reference in the SAR ADC chip is only 449×614 μm². The total power consumption is only 1.092 mW.     

新三维非线性混沌系统的动力学特性分析

基于动力系统的理论和方法,结合理论分析和Matlab仿真,利用微分方程比较定理和多元函数的Lagrange 乘数法,研究了一类新混沌系统的最终界和全局指数吸引集.对于系统的任意参数,分别得到了该混沌系统最终界和全局吸引集统一的数学表达式.最后,Matlab模拟验证了理论结果的正确性.为该系统的混沌控制、混沌同步、混沌吸引子维数的估计提供了理论依据.     

PET成像前端读出芯片研究进展

在过去的半个多世纪里,虽然正电子发射断层(PET)成像设备在外型上没有多大变化,但在技术和方法上发生了多次革命性的飞跃。微电子技术在PET成像领域的应用将进一步推动PET向更小体积、更高性能、更低成本等方向发展。从PET系统成像原理出发,详细综述了PET前端读出芯片技术的研究进展。将PET探测器信号的前端读出和信号处理分为光电转换、信号采集、脉冲高度分析、峰值探测和保持、信号数字化和数字信号处理等环节,给出了各个环节的微电子电路实现。然后,描述了PET前端读出大规模专用集成电路的研发进展,指出采用数字电路的方法来处理探测器前端读出和模拟信号处理已经成为PET前端电子的发展趋势,而且集成PET专用DSP的多通道智能前端读出电路已经成为一个重要的方向。     

应用于前端读出电路的片上LDO设计

为满足辐射探测器前端读出电路对模拟电路稳压器片上集成和快速瞬态时间响应的需求,设计了一种基于0.18μm CMOS工艺的全片上集成LDO。采用大摆幅高增益放大器驱动输出功率管,增大了功率管栅极调节电压摆幅,减小了功率管尺寸和LDO压差电压。该放大器同时增大了LDO的环路增益和对功率管栅极的充放电电流,从而改善了瞬态响应性能。为了不牺牲环路增益带宽和芯片面积,并且保证LDO在整个负载电流区间内保持稳定,提出了一种负载电流分区频率补偿方法。仿真结果表明,在负载电容为200 nF,负载电流范围为0～200 mA时,设计的LDO相位裕度均大于53^o。在相同功率管尺寸情况下,采用大摆幅高增益放大器可以将LDO最大输出电流能力提高到两倍以上。当负载电流从10 mA跳变到200 mA时,LDO输出电压恢复时间小于6.5μs。设计的LDO电路面积为120μm×264μm,满载时电源效率为97.76%,最小压差电压为50 mV。     

Design and performances of a low-noise and radiation-hardened readout ASIC for CdZnTe detectors

In this paper, we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit (ASIC) dedicated to CdZnTe detectors for a hard X-ray imager in space applications. The readout channel is comprised of a charge sensitive amplifier, a CR-RC shaping amplifier, an analog output buffer, a fast shaper, and a discriminator. An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2×2.2 mm². The input energy range is from 5 to 350 keV. For this 8-channel prototype ASIC, the measured electrical characteristics are as follows:the overall gain of the readout channel is 210 V/pC, the linearity error is less than 2%, the crosstalk is less than 0.36%, The equivalent noise charge of a typical channel is 52.9 e^- at zero farad plus 8.2 e^- per picofarad, and the power consumption is less than 2.4 mW/channel. Through the measurement together with a CdZnTe detector, the energy resolution is 5.9% at the 59.5-keV line under the irradiation of the radioactive source ²⁴¹Am. The radiation effect experiments show that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad(Si).     

A simplified compact model of miniaturized cross-shaped CMOS integrated Hall devices

A simplified compact model for a miniaturized cross-shaped CMOS integrated Hall device is presented.The model has a simple circuit structure,only consisting of a passive network with eight non-linear r...     

用于威尔金森A/D转换器的高速高精度比较器

提出了一种用于威尔金森(Wilkinson) A/D转换器(ADC)的高速高精度比较器的设计方法.该比较器由三级预放大器和一级输出放大器组成,采用开环结构和多级级联的形式,以满足增益和速度的要求.为了消除失调电压对电路的影响,采用输出失调消除技术进行失调电压校正.采用3.3 V TSMC 0.18 μm CMOS工艺完成电路设计.Spectre仿真结果表明,在1 MHz最高采样频率下,该比较器的分辨率达到0.4 mV,传输延迟小于20 ns,满足12位Wilkinson ADC的要求.     

CMOS场效应晶体管的发展趋势

自从1947年第一支晶体管的发明，半导体集成电路在二十世纪的后三十年有了一个极大的发展。这个发展极大的推动了世界性的产业革命和人类社会的进步。今天在我们每个人的日常生活中，英特网，手机的普及和计算机在各个领域的大量应用，已经使我们进入了信息时代。在这中间起决定性作用的是在硅晶片上工作的CMOS场效应晶体管的发明.