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片上变压器是在硅片上制造的空心变压器,具有高耦合系数、低功耗和可集成性,与传统的隔离器相比,基于片上变压器的数字隔离器在功耗、体积、传输速率等方面具有明显优势。通过3D仿真方法研究了片上变压器的几何尺寸对变压器性能参数的影响,得到了优化后的片上变压器设计参数。采用自主开发的工艺流程流片,研制了片上变压器样片。同时,介绍了一种与片上变压器相匹配的编解码电路原理和设计方法,研制出磁偶数字隔离器芯片。测试结果表明,磁偶数字隔离器芯片耐压隔离能力超过3 500 V,可实现0~40 Mibit/s的低功耗数据隔离传输,延迟时间为20 ns,脉宽失真<3 ns,验证了片上变压器设计的正确性。 相似文献
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A semi-digital clock and data recovery (CDR) is presented. In order to lower CDR trace jitter and decrease loop latency, an average-based phase detection algorithm is adopted and realized with a novel circuit. Implemented in a 0.13 μm standard 1P8M CMOS process, our CDR is integrated into a high speed serial and de-serial (SERDES) chip. Measurement results of the chip show that the CDR can trace the phase of the input data well and the RMS jitter of the recovery clock in the observation pin is 122 ps at 75 MHz clock frequency, while the bit error rate of the recovery data is less than 10 × 10-12. 相似文献
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GPS多天线测姿系统的历元连续模糊度解算 总被引:1,自引:0,他引:1
在实时姿态参数测量中,GPS载波相位测量模糊度的解算,是制约成功的关键问题,本文从分析多天线配置入手,提出了每个历元连续模糊度的解决办法。 相似文献
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A semi-digital clock and data recovery(CDR) is presented.In order to lower CDR trace jitter and decrease loop latency,an average-based phase detection algorithm is adopted and realized with a novel circuit. Implemented in a 0.13μm standard 1P8M CMOS process,our CDR is integrated into a high speed serial and de-serial(SERDES) chip.Measurement results of the chip show that the CDR can trace the phase of the input data well and the RMS jitter of the recovery clock in the observation pin is 122 ps at 75 MHz clock frequency,while the bit error rate of the recovery data is less than 10×10-12. 相似文献
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设计了一种基于片上变压器的隔离式DC-DC开关电源。通过分析影响开关电源能量转换效率的因素,设计了一种应用于隔离式DC-DC开关电源的LC振荡器,提高了隔离式开关电源的整体效率。采用CSMC 0.35 μm BCD工艺进行设计,并将该振荡器应用于隔离式开关电源。隔离式开关电源的输入电压为3.3 V,输出电压为5 V。仿真结果表明,时钟振荡频率为180 MHz,应用该振荡器的DC-DC开关电源最大输出电流达到62 mA,转换效率提高到35.6%。 相似文献
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