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This paper presents a high-speed column-parallel cyclic analog-to-digital converter(ADC) for a CMOS image sensor.A correlated double sampling(CDS) circuit is integrated in the ADC,which avoids a stand-alone CDS circuit block.An offset cancellation technique is also introduced,which reduces the column fixed-pattern noise(FPN) effectively.One single channel ADC with an area less than 0.02 mm~2 was implemented in a 0.13μm CMOS image sensor process.The resolution of the proposed ADC is 10-bit,and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively.The power consumption from 3.3 V supply is only 0.66 mW.An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels.The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors. 相似文献
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This paper presents a novel compact memory in the processing element (PE) for single-instruction multiple-data (SIMD) vision chips. The PE memory is constructed with 8×8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm^2/bit promises a higher integration level of the processor. A prototype chip with a 64×64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction. 相似文献
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本文提出了一种兼容测距成像的图像传感器控制器,其测距原理基于采用连续波调制的飞行时间测距技术。控制器用于产生256×256高速CMOS图像传感器所需的可配置控制信号。图像传感器具有普通成像和测距成像两种工作模式,在两种工作模式下,通过配置参数产生的控制时序可以实现行滚动曝光与数字域的相关双采样。在逻辑电路级采用优化的设计方法,使得芯片面积和功耗得到优化。图像传感器控制器采用0.18 μm CMOS标准工艺制造,芯片面积为700×3380 μm2。在1.8 V供电电压和100 MHz工作频率下,由综合工具估算出的动态功耗为65 mW。测试结果验证了图像传感器控制器产生控制时序的功能。 相似文献
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