内嵌SCR的LDMOS器件双骤回ESD特性研究

基于寄生参数分析,对内嵌SCR的LDMOS器件给出了二次骤回发生判据。本文对三种典型结构进行了数值仿真和比较,并基于此判据仿真优化了影响二次骤回的器件结构参数,从而提高器件ESD性能。TLP试验数据表明,当二次骤回电压由25.4V降低到8.1V时,器件ESD泄放能力由0.57A提高到3.1A。     

ESD robustness studies on the double snapback characteristics of an LDMOS with an embedded SCR

Criterion for the second snapback of an LDMOS with an embedded SCR is given based on parasitic parameter analysis.According to this criterion,three typical structures are compared by numerical simulation and structural parameters which influence the second snapback are also analyzed to optimize the ESD characteristics. Experimental data showed that,as the second snapback voltage decreased from 25.4 to 8.1 V,the discharge ability of the optimized structure increased from 0.57 to 3.1 A.     

一种用于混合电压芯片的新型ESD防护触发电路

为了降低芯片成本,通过使用低压器件串联的方式构造静电防护触发电路,使芯片在没有使用高压I/O器件的情况下实现了高压电源域的ESD防护。由于该触发电路未使用电容器件,因此有效地降低了ESD触发电路所占用的芯片面积,并且该电路为静态电压触发,其开启时间可远长于一般电容电阻耦合的触发电路。通过在HSPICE中使用类ESD(ESD-like)的方波脉冲,可以看出该电路在发生ESD时能有效地触发ESD器件,而在芯片正常工作时不易因外界干扰而产生误触发。     

A novel NLDMOS with a high ballast resistance for ESD protection

To prevent the non-uniform conduction phenomenon caused by the Kirk effect in an NLDMOS under ESD stress, a novel NLDMOS structure is proposed. High electron injection current is the base of Kirk effect. Higher electron injection can makes the Kirk effect more serious and lead easily to the non-uniform conduction phenomenon. By splitting the drain N＋ with the field oxide in the proposed structure, the crowded current can lead to a higher voltage drop on the ballast resistance. Therefore, the non-uniform conduction is suppressed, and its failure current is much improved.     

LDMOS器件源-衬版图结构优化对ESD性能影响的研究

To enhance the robustness of LDMOS ESD protection devices, the influence of a source-bulk layout structure is analyzed by theoretical analysis and numerical simulation. Novel structures with varied source-bulk layout structures are fabricated and compared. As demonstrated by TLP testing, the optimized structure has an 88% larger It2 than a conventional one, and its Vtl is reduced from 55.53 to 50.69 V.     

5V CMOS中GGNMOS ESD失效电流和沟道长度正向关系的分析

Contrary to general understanding,a test result shows that devices with a shorter channel length have a degraded ESD performance in the advanced silicided CMOS process.Such a phenomenon in a gate-grounded NMOSFET(GGNMOS) was investigated,and the current spreading effect was verified as the predominant factor. Due to transmission line pulse(TLP) measurements and Sentaurus technology computer aided design(TCAD) 2-D numerical simulations,parameters such as current gain,on-resistance and power density were discussed in detail.     

寄生电阻对高压器件ESD性能的影响

本文从理论上分析了衬底寄生电阻以及漏端镇流电阻对高压LDMOS器件ESD特性的影响。文中采用了多种结构对上述参数进行优化,并将其在0.35μm BCD工艺下进行试验,测试结果表明增加寄生电阻可以有效地提高器件的ESD泄放能力,最优结构的二次击穿电流由原始器件的0.75A增大到3.5A,即泄放电流增加了367%。