抗辐射加固版图技术的性能比较

Total ionizing dose （TID） effect and single event effect （SEE） from space may cause serious effects on bulk silicon and silicon on insulator （SOl） devices, so designers must pay much attention to these bad effects to achieve better performance. This paper presents different radiation-hardened layout techniques to mitigate TID and SEE effect on bulk silicon and SOl device and their corresponding advantages and disadvantages are studied in detail. Under 0.13μm bulk silicon and SOl process technology, performance comparisons of two different kinds of DFF circuit are made, of which one kind is only hardened in layout （protection ring for bulk silicon DFF, T-gate for SO! DFF）, while the other kind is also hardened in schematic such as DICE structure. The result shows that static power and leakage of SOI DFF is lower than that of bulk silicon DFF, while SOI DFF with T-gate is a little slower than bulk silicon DFF with protection ring, which will provide useful guidance for radiation-hardened circuit and layout design.     

一种应用于超宽带系统的宽带LNA的设计

结合切比雪夫滤波器,可以实现宽带输入匹配的特性和片上集成窄带低噪声放大器(LNA)的噪声优化方法。提出一套完整的基于CMOS工艺的宽带LNA的设计流程,并设计了一个应用于超宽带(UWB)系统的3~5 GHz宽带LNA电路。模拟结果验证了设计流程的正确性。该电路采用SMIC 0.18μm CMOS工艺进行模拟仿真。结果表明,该LNA带宽为3~5 GHz,功率增益为5.6 dB,带内增益波动1.2dB,带内噪声系数为3.3~4.3 dB,IIP3为-0.5 dBm;在1.8V电源电压下,主体电路电流消耗只有9 mA,跟随器电流消耗2 mA,可以驱动1.2 pF容性负载。