A 0.6 V 10 bit 1 MS/s monotonic switching SAR ADC with common mode stabilizer in 0.13 μm CMOS

This paper presents a 0.6 V 10 bit successive approximation register （SAR） ADC design dedicated to the wireless sensor network application. It adopts a monotonic switching scheme in the DAC to save chip area and power consumption. The main drawback of the monotonic switching scheme is its large common mode shift and the associated comparator offset variation. Due to the limited headroom at the 0.6 V supply voltage, the conventional constant current biasing technique cannot be applied to the dynamic comparator. In this design, a common mode stabilizer is introduced to address this issue in low-voltage design. The effectiveness of this method is verified through both simulation and measurement results. Fabricated with 1P8M 0.13 μm CMOS technology, the proposed SAR ADC consumes 6.3 μW at 1 MS/s from a 0.6 V supply, and achieves 51.25 dB SNDR at the Nyquist frequency and FOM of 21 fJ/conversion-step. The core area is only 120 × 300 μm^2.     

A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process

This paper presents a 10-bit 50-MS/s subrange successive-approximation register (SAR) analog-to-digital converter (ADC) composed of a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC. In the coarse ADC, multi-comparator SAR architecture is used to reduce the digital logic propagation delay, and a traditional asynchronous SAR ADC with monotonic switching method is used as the fine ADC. With that combination, power dissipation also can be much reduced. Meanwhile, a modified SAR control logic is adopted in the fine ADC to speed up the conversion and other techniques, such as splitting capacitors array, are borrowed to reduce the power consumption. Fabricated with 1P8M 130-nm CMOS technology, the proposed SAR ADC achieves 51.6-dB signal to noise and distortion ratio (SNDR) and consumes 186 μ W at 50 MS/s with a 1-V supply, resulting in a figure of merit (FOM) of 12 fJ/conversion-step. The core area is only 0.045 mm².     

一种低电源电压敏感度伪差分环形振荡器

基于0.18 μm CMOS工艺,提出了一种低电源电压敏感度的环形振荡器电路。分析了电源噪声和衬底噪声的产生与耦合机制,以应对相位噪声的影响。对二级伪差分环形振荡器的电源电压敏感度进行了定量分析。基于分析结果,设计了基于电流源的补偿偏置电路,有效降低了环形振荡器的电源电压敏感度。后端仿真结果表明,振荡器的电源电压敏感度达到0.05%@1% VDD,功耗为4.5 mW。     

一种基于共模稳定电路的单调开关切换的0.6V 10位 1MHz采样率的逐次逼近型模数转换器

本文叙述了一个在0.6V电源电压下用于无线传感网络中的10位逐次逼近型模数转换器（SAR ADC）的设计。这个SAR ADC中的数模转换器（DAC）采用单调开关切换的方式,目的是减小芯片面积和功耗。但是单调开关切换的方式存在共模电压改变引起的比较器失调电压动态变化的问题。由于电源电压仅有0.6V,传统的在动态比较器中使用恒定电流偏置技术的方法不再适用。在本文的设计中,我们提出了一个共模电压稳定电路（common mode stabilizer）可在低电源电压下稳定比较器的输入共模电压,这种方法的有效性得到了仿真和测试的验证。本文设计的SAR ADC采用0.13μm CMOS工艺,测试结果显示在0.6V电源电压和1MHz采样率下,功耗为6.3μW,在奈奎斯特输入频率下信号噪声失真比（SNDR）为51.25 dB,品质因数（FOM）为21 fJ/conversion-step,芯片的核心面积只有120 μm×300 μm。