一种带有插值滤波器的8位650MHz采样速率数字模拟转换器

针对OFDM-UWB标准超宽带收发系统中数模转换器(DAC)的要求,设计了一款8位650MHz采样速率电流驱动型数模转换器(Current-steering DAC)。为了提高静态性能,本设计通过蒙特卡洛分析确定电流源最佳尺寸并采用双中心版图技术;为了提高动态性能,文中采用共源共栅电流源结构,对开关电压降摆幅处理并在数字输入端前加入插值滤波器。测试结果表明,DAC的积分非线性(INL)和差分非线性(DNL)分别为0.3LSB和0.41LSB,650MHz转换速率下带内奈奎斯特无杂散动态范围(SFDR)为41dB。整体面积为1.8cm×1.3cm,其中DAC面积为0.8cm×0.8cm。     

一个适用于多通道时间交织模数转换器采样时间误差校准算法的数模转换器

A sampling switch with an embedded digital-to-skew converter(DSC) is presented.The proposed switch eliminates time-interleaved ADCs’ skews by adjusting the boosted voltage.A similar bridged capacitors’ charge sharing structure is used to minimize the area.The circuit is fabricated in a 0.18μm CMOS process and achieves sub-1 ps resolution and 200 ps timing range at a rate of 100 MS/s.The power consumption is 430μW at maximum.The measurement result also includes a 2-channel 14-bit 100 MS/s time-interleaved ADCs(TI-ADCs) with the proposed DSC switch’s demonstration.This scheme is widely applicable for the clock skew and aperture error calibration demanded in TI-ADCs and SHA-less ADCs.