Process optimization of a deep trench isolation structure for high voltage SOI devices

In this work, the process reasons for weak point formation of the deep trench on SOI wafer have been analyzed in detail. The optimized trench process is also proposed. It is found that there are two main reasons: one is over-etching laterally of silicon on the surface of buried oxide caused by fringe effect; the other is slowly growth rate of isolation oxide in the concave silicon corner of trench bottom. In order to improve the isolation performance of deep trench, two feasible ways for optimizing trench process are proposed. The improved process thickens the isolation oxide and rounds sharp silicon corner at weak point, increasing the applied voltage by 15-20V at the same leakage current. The proposed new trench isolation process has been verified in foundry’s 0.5-μm HV SOI technology.     

Double RESURF nLDMOS功率器件的优化设计

基于漂移区表面具有单个P-top层Double RESURF nLDMOS的结构和耐压机理,提出了具有P-top层终端结构的Double RESURF nLDMOS结构,并通过利用SENTAURUS TSUPREM4和DEVICES软件进行优化设计。P-top层终端结构不仅降低了击穿电压对P-top层参数的敏感度,而且在漂移区引入一个附加的电场峰值,使漂移区电场分布进一步趋于平坦化。与传统Single RESURF和普通Double RESURF器件相对比,击穿电压可以分别提高约13.5%和4%,导通电阻却提高了11.8%和6%,但在满足击穿电压相等的条件下,该结构通过控制P-top层的位置和漂移区剂量可以使导通电阻降低约37%。     

Process optimization of a deep trench isolation structure for high voltage SOI devices

The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail.An optimized trench process is also proposed.It is found that there are two main reasons:one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect;and the other is the slow growth rate of the isolation oxide in the concave silicon corner of the trench bottom.In order to improve the isolation performance of the deep trench,two feasible ways for optimizi...