基于SRAM的通用存算一体架构平台在物联网中的应用

最近,存算一体(IMC)架构引起了广泛关注,并被认为有望成为突破冯诺依曼瓶颈的新型计算机架构,特别是在数据密集型(data-intensive)计算中能够带来显著的性能和功耗优势.其中,基于SRAM的IMC架构方案也被大量研究与应用.该文在一款基于SRAM的通用存算一体架构平台——DM-IMCA的基础上,探索IMC架构在物联网领域中的应用价值.具体来说,该文选取了物联网中包括信息安全、二值神经网络和图像处理在内的多个轻量级数据密集型应用,对算法进行分析或拆分,并将关键算法映射到DM-IMCA中的SRAM中,以达到加速应用计算的目的.实验结果显示,与基于传统冯诺依曼架构的基准系统相比,利用DM-IMCA来实现物联网中的轻量级计算密集型应用,可获得高达24倍的计算加速比.     

基于SRAM的通用存算一体架构平台在物联网中的应用

最近,存算一体(IMC)架构引起了广泛关注,并被认为有望成为突破冯诺依曼瓶颈的新型计算机架构,特别是在数据密集型(data-intensive)计算中能够带来显著的性能和功耗优势.其中,基于SRAM的IMC架构方案也被大量研究与应用.该文在一款基于SRAM的通用存算一体架构平台——DM-IMCA的基础上,探索IMC架构...     

A monolithic integrated low-voltage deep brain stimulator with wireless power and data transmission

A monolithic integrated low-voltage deep brain stimulator with wireless power and data transmission is presented. Data and power are transmitted to the stimulator by mutual inductance coupling, while the in-vitro controller encodes the stimulation parameters. The stimulator integrates the digital control module and can generate the bipolar current with equal amplitude in four channels. In order to reduce power consumption, a novel controlled threshold voltage cancellation rectifier is proposed in this paper to provide the supply voltage of the stimulator. The monolithic stimulator was fabricated in a SMIC 0.18 μm 1-poly 6-metal mixed-signal CMOS process, occupying 0.23 mm², and consumes 180 μW on average. Compared with previously published stimulators, this design has advantages of large stimulated current (0-0.8 mA) with the double low-voltage supply (1.8 and 3.3 V), and high-level integration.