OEIC光接收机研究的湿法选择腐蚀

试验了用柠檬酸与双氧水系列腐蚀液来实现ＩｎＡｌ（Ｇａ）Ａｓ∶ＩｎＰ和ＩｎＧａＡｓ∶ＩｎＡｌＡｓ的选择腐蚀,达到了较好的效果,且工艺重复性好。同一单片上ＭＳＭ（金属－半导体－金属）光探测器的光响应度可达到０．５Ａ／Ｗ,ＨＥＭＴ器件最大跨导为３０５ｍＳ／ｍｍ,最大饱和电流密度为３５０ｍＡ／ｍｍ。完成了实现ＯＥＩＣ光接收机的关键一步。     

1.25Gb/s InP基多量子阱激光器与HBT驱动电路的单片集成

描述了一种基于InP材料沿[011]晶向湿法化学腐蚀形成平滑侧壁实现的InP基多量子阱激光器和异质结双极晶体管驱动电路单片集成.通过一个横向缓冲台面结构,降低了激光器阳极和晶体管集电极互连工艺的难度,改善了光发射单片光电集成电路的可制造性.采用该方法制作的光发射单片直流功耗为120mW,在码长223-1传输速率1.5Gb/s伪随机码信号调制下有清晰的眼图,光输出功率为2dBm.     

Plasma-assisted surface treatment for low-temperature annealed ohmic contact on AlGaN/GaN heterostructure field-effect transistors

In this study, a low-temperature annealed ohmic contact process was proposed on Al Ga N/Ga N heterostructure field effect transistors(HFETs) with the assistance of inductively coupled plasma(ICP) surface treatment. The effect of ICP treatment process on the 2DEG channel as well as the formation mechanism of the low annealing temperature ohmic contact was investigated. An appropriate residual Al Ga N thickness and a plasma-induced damage are considered to contribute to the low-temperature annealed ohmic contact. By using a single Al layer to replace the conventional Ti/Al stacks, ohmic contact with a contact resistance of 0.35 ?·mm was obtained when annealed at 575?C for 3 min. Good ohmic contact was also obtained by annealing at 500?C for 20 min.     

InP基InAlAs—InAs HEMT

对ＩｎＡｓ沟道ＩｎＡｌＡｓ－ＩｎＡｓ高电子迁移率晶体管材料及器件的设计和器件制作工艺进行了研究，器件样品性能良好，１μｍ栅长ＩｎＡｌＡｓ－ＩｎＡｓ ＨＥＭＴ器件的最大跨导３００Ｋ时达到２５０ｍＳ／ｍｍ。这是国内首次研制成功的ＩｎＡｓ沟道ＨＥＭＴ器件。     

与CMOS-SEED灵巧象素相关的倒装焊工艺

介绍了新型ＣＭＯＳ－ＳＥＥＤ灵巧象素结构原理及相关的倒装焊技术,采用厚光致抗蚀剂作掩模,通过磁控溅射和真空蒸发相结合,解决了与ＣＭＯＳ－ＳＥＥＤ有关的Ｉｎ凸点阵列成型等关键工艺,并用Ｍ８－Ａ型可视对准式倒装焊系统完成了ＣＭＯＳ电路芯片和ＳＥＥＤ阵列芯片的倒装焊。     

超低功耗GaAs PHEMT跨阻前置放大器

本文报导了光纤通信接收机中GaAs PHEMT工艺前置放大器的设计方法与测试结果。此前置放大器采用单电源供电，由1级放大、2级源级跟随器和1个反馈电阻组成。当前置放大器工作在2.5Gbit/s时，跨阻可达60dB Ω。采用 5V电源供电，功耗为110mW。     

Hybrid-anode structure designed for a high-performance quasi-vertical GaN Schottky barrier diode

A quasi-vertical GaN Schottky barrier diode with a hybrid anode structure is proposed to trade off the on-resistance and the breakdown voltage. By inserting a SiN dielectric between the anode metal with a relatively small length, it suppresses the electric field crowding effect without presenting an obvious effect on the forward characteristics. The enhanced breakdown voltage is ascribed to the charge-coupling effect between the insulation dielectric layer and GaN. On the other hand, the current density is decreased beneath the dielectric layer with the increasing length of the SiN, resulting in a high on-resistance. Furthermore, the introduction of the field plate on the side wall forms an metal-oxide-semiconductor (MOS) channel and decreases the series resistance, but also shows an obvious electric field crowding effect at the bottom of the mesa due to the quasi-vertical structure.     

Evaluation of a gate-first process for AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with low ohmic annealing temperature

In this paper, TiN/AlO_x gated Al Ga N/Ga N metal–oxide–semiconductor heterostructure field-effect transistors(MOSHFETs) were fabricated for gate-first process evaluation. By employing a low temperature ohmic process, ohmic contact can be obtained by annealing at 600℃ with the contact resistance approximately 1.6 ?·mm. The ohmic annealing process also acts as a post-deposition annealing on the oxide film, resulting in good device performance. Those results demonstrated that the TiN/AlO_x gated MOS-HFETs with low temperature ohmic process can be applied for self-aligned gate Al Ga N/Ga N MOS-HFETs.     

Self-aligned-gate AlGaN/GaN heterostructure field-effect transistor with titanium nitride gate

Self-aligned-gate heterostructure field-effect transistor(HFET) is fabricated using a wet-etching method.Titanium nitride(TiN) is one kind of thermal stable material which can be used as the gate electrode.A Ti/Au cap layer is fixed on the gate and acts as an etching mask.Then the T-shaped gate is automatically formed through over-etching the TiN layer in 30% H_2O_2 solution at 95 ℃.After treating the ohmic region with an inductively coupled plasma(ICP) method,an Al layer is sputtered as an ohmic electrode.The ohmic contact resistance is approximately 0.3 Ω·mm after annealing at a low-temperature of 575 ℃ in N_2 ambient for 1 min.The TiN gate leakage current is only 10~(-8) A after the low-temperature ohmic process.The access region length of the self-aligned-gate(SAG) HFET was reduced from 2 μm to 0.3 μm compared with that of the gate-first HFET.The output current density and transconductance of the device which has the same gate length and width are also increased.     

Design of vertical diamond Schottky barrier diode with junction terminal extension structure by using the n-Ga2O3/p-diamond heterojunction

A novel junction terminal extension structure is proposed for vertical diamond Schottky barrier diodes (SBDs) by using an n-Ga₂O₃/p-diamond heterojunction. The depletion region of the heterojunction suppresses part of the forward current conduction path, which slightly increases the on-resistance. On the other hand, the reverse breakdown voltage is enhanced obviously because of attenuated electric field crowding. By optimizing the doping concentration, length, and depth of n-Ga₂O₃, the trade-off between on-resistance and breakdown voltage with a high Baliga figure of merit (FOM) value is realized through Silvaco technology computer-aided design simulation. In addition, the effect of the work functions of the Schottky electrodes is evaluated. The results are beneficial to realizing a high-performance vertical diamond SBD.