排序方式: 共有21条查询结果,搜索用时 0 毫秒
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介绍了subLVDS接口的系统结构并给出一种改进的内部收发器实现电路.为了稳定直流工作点,在发送器内部加入与电源电压无关的自偏置电压源和共模负反馈电路;通过轨到轨预放大器,接收器的共模输入电压可以达到电源至地的范围.SMIC0.18μm 1P6M的工艺下,仿真结果表明该系统对随机输入数据的工作速度可以达到1.5Gb/s,工作温度范围为-40~120℃. 相似文献
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Frequency synthesizer is an important part of optical and wireless communication system. Low power comsumption prescaler is
one of the most critical unit of frequency synthesizer. For the frequency divider, it must be programmable for channel selection
in multi-channel communication systems. A dual-modulus prescaler (DMP) is needed to provide variable division ratios. DMP
is considered as a critical power dissipative block since it always operates at full speed. This paper introduces a high speed
and low power complementary metal oxide semiconductor (CMOS) 15/16 DMP based on true single-phase-clock (TSPC) and transmission
gates (TGs) cell. A conventional TSPC is optimized in terms of devices size, and it is resimulated. The TSPC is used in the
synchronous and asynchronous counter. TGs are used in the control logic. The DMP circuit is implemented in 0.18 μm CMOS process.
The simulation results are provided. The results show wide operating frequency range from 7.143 MHz to 4.76 GHz and it comsumes
3.625 mW under 1.8 V power supply voltage at 4.76 GHz. 相似文献
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提出了一种高电源纹波抑制比的低压差线性稳压器.该低压差线性稳压器通过提高带隙基准的电源抑制比以达到提高LDO(低压差线性稳压器)低频电源纹波抑制的能力.在TSMC 0.18μm CMOS工艺下进行了仿真验证,仿真结果表明,该LDO最大负载电流可以达到80mA,当负载电流在0~80mA范围内变化时,开环相位裕度均大于64°,证明了低压差线性稳压器的高稳定性.当负载电流从0mA跳变到80mA时,系统的输出电压过冲仅为15mV,环路响应时间仅为0.5μs.当负载电流为80mA,测得10kHz时的电源纹波抑制比为-60.82dB,100kHz时LDO的电源纹波抑制比为-57.66dB. 相似文献
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This paper describes a CMOS voltage reference using only resistors and transistors working in weak inversion,without the need for any bipolar transistors.The voltage reference is designed and fabricated by a 0.18μm CMOS process.The experimental results show that the proposed voltage reference has a temperature coefficient of 370 ppm/℃at a 0.8 V supply voltage over the temperature range of-35 to 85℃and a 0.1%variation in supply voltage from 0.8 to 3 V.Furthermore,the supply current is only 1.5μA at 0.8 V supply voltage. 相似文献
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采用ASMC0.35μm CMOS工艺设计了低功耗、高电源抑制比(PSRR)、低温漂、输出1V的带隙基准源电路。该设计中,偏置电压采用级联自偏置结构,运放的输出作为驱动的同时也作为自身电流源的驱动,实现了与绝对温度成正比(PTAT)温度补偿。通过对其进行仿真验证,当温度在-40~125℃和电源电压在1.6~5V时,输出基准电压具有3.68×10-6/℃的温度系数,Vref摆动小于0.094mV;在低频时具有-114.6dB的PSRR,其中在1kHz时为-109.3dB,在10kHz时为-90.72dB。 相似文献
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SOC用400-800MHz锁相环IP的设计 总被引:4,自引:0,他引:4
设计了一个基于锁相环结构、可应用于SOC设计的时钟产生模块.电路输出频率在400~800 MHz,使用SMIC 0.18 μm CMOS工艺进行流片.芯片核心模块工作电压为1.8 V和3.3 V.根据Hajimi关于VCO中抖动(jitter)的论述,为了降低输出抖动,采用一种全差动、满振幅结构的振荡器;同时,通过选取合适的偏置电流,实现对环路带宽的温度补偿.流片后测试结果为:输出频率范围400~800 MHz,输入频率40~200 MHz;在输出频率为800 MHz时,功耗小于23 mA,周期抖动峰峰值为62.5 ps,均方根(rms)值为13.1 ps,芯片面积0.6 mm2. 相似文献
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设计了一种时钟产生电路,该电路采用基于低功耗锁相环(PLL)的方法,用于产生13.56MHz ASK100%、10%调制射频卡所需要的时钟。针对射频识别(RFID)系统,锁相环采取了特殊的设计。本电路作为模块可应用于符合ISO/IEC15693、ISO/IEC18000-3标准的非接触IC卡中。通过Cadence spectre软件,使用0.35μm互补金属氧化物半导体(CMOS)工艺模型进行验证。仿真结果显示:电路采用3.3V电源供电时,100%调制载波幅度为0%时,总工作电流仅为17μA。 相似文献
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