In-situ SiN combined with etch-stop barrier structure for high-frequency AlGaN/GaN HEMT

The etch-stop structure including the in-situ SiN and AlGaN/GaN barrier is proposed for high frequency applications.The etch-stop process is realized by placing an in-situ SiN layer on the top of the thin AlGaN barrier.F-based etching can be self-terminated after removing SiN,leaving the AlGaN barrier in the gate region.With this in-situ SiN and thin barrier etch-stop structure,the short channel effect can be suppressed,meanwhile achieving highly precisely controlled and low damage etching process.The device shows a maximum drain current of 1022 mA/mm,a peak transconductance of 459 mS/mm,and a maximum oscillation frequency(fmax)of 248 GHz.     

A study on Al2O3 passivation in GaN MOS-HEMT by pulsed stress

This paper studies systematically the drain current collapse in AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors （MOS-HEMTs） by applying pulsed stress to the device. Low-temperature layer of Al2O3 ultrathin film used as both gate dielectric and surface passivation layer was deposited by atomic layer deposition （ALD）. For HEMT, gate turn-on pulses induced large current collapse. However, for MOS-HEMT, no significant current collapse was found in the gate turn-on pulsing mode with different pulse widths, indicating the good passivation effect of ALD Al2O3. A small increase in Id in the drain pulsing mode is due to the relieving of self-heating effect. The comparison of synchronously dynamic pulsed Id - Vds characteristics of HEMT and MOS-HEMT further demonstrated the good passivation effect of ALD Al2O3.     

The degradation mechanism of an AlGaN/GaN high electron mobility transistor under step-stress

Step-stress experiments are performed in this paper to investigate the degradation mechanism of an AlGaN/GaN high electron mobility transistor(HEMT).It is found that the stress current shows a recoverable decrease during each voltage step and there is a critical voltage beyond which the stress current starts to increase sharply in our experiments.We postulate that defects may be randomly induced within the AlGaN barrier by the high electric field during each voltage step.But once the critical voltage is reached,the trap concentration will increase sharply due to the inverse piezoelectric effect.A leakage path may be introduced by excessive defect,and this may result in the permanent degradation of the AlGaN/GaN HEMT.     

功率MOSFET的负偏置温度不稳定性效应中的平衡现象

通过对功率金属氧化物半导体场效应晶体管在静态应力下的负偏置温度不稳定性的实验研究, 发现器件参数的退化随时间的关系遵循反应扩散模型所描述的幂函数关系, 并且在不同栅压应力下, 实验结果中均可观察到平台阶段的出现. 基于反应扩散理论的模型进行了仿真研究, 通过仿真结果分析和验证了此平台阶段对应于反应平衡阶段, 并且解释了栅压应力导致平台阶段持续时间不同的原因. 关键词： 功率金属氧化物半导体场效应晶体管 负偏置温度不稳定性 反应扩散模型     

Electric-stress reliability and current collapse of different thickness SiNx passivated AlGaN/GaN high electron mobility transistors

This paper investigates the impact of electrical degradation and current collapse on different thickness SiNx passivated AlGaN/GaN high electron mobility transistors.It finds that higher thickness SiNx passivation can significantly improve the high-electric-field reliability of a device.The degradation mechanism of the SiNx passivation layer under ON-state stress has also been discussed in detail.Under the ON-state stress,the strong electric-field led to degradation of SiNx passivation located in the gate-drain region.As the thickness of SiNx passivation increases,the density of the surface state will be increased to some extent.Meanwhile,it is found that the high NH 3 flow in the plasma enhanced chemical vapour deposition process could reduce the surface state and suppress the current collapse.     

High power-added-efficiency AlGaN/GaN HEMTs fabricated by atomic level controlled etching

An atomic-level controlled etching(ACE)technology is invstigated for the fabrication of recessed gate AlGaN/GaN high-electron-mobility transistors(HEMTs)with high power added efficiency.We compare the recessed gate HEMTs with conventional etching(CE)based chlorine,Cl₂-only ACE and BCl³/Cl₂ACE,respectively.The mixed radicals of BCl₃/Cl₂were used as the active reactants in the step of chemical modification.For ensuring precise and controllable etching depth and low etching damage,the kinetic energy of argon ions was accurately controlled.These argon ions were used precisely to remove the chemical modified surface atomic layer.Compared to the HEMTs with CE,the characteristics of devices fabricated by ACE are significantly improved,which benefits from significant reduction of etching damage.For BCl₃/Cl₂ACE recessed HEMTs,the load pull test at 17 GHz shows a high power added efficiency(PAE)of 59.8%with an output power density of 1.6 W/mm at Vd=10 V,and a peak PAE of 44.8%with an output power density of 3.2 W/mm at Vd=20 V in a continuous-wave mode.     

Fe39.4－xCo40Si9B9Nb2.6Cux纳米晶合金的有效磁各向异性研究

采用多晶材料趋近饱和定律研究了非晶Fe_39.4-xCo₄₀Si₉B₉Nb_2.6Cu_x(x=0.5,1,1.5) 合金在不同温度纳米晶化后的有效磁各向异性常数〈K〉.结果表明， Cu含量较低(x=0.5)时，纳米晶粒较大并且在较低的退火温度(550℃)下析出硬磁相，〈K〉随退火温度T_a升高显著增加；随着Cu含量的增加，有效地细化了晶粒，并且抑制了硼化物的析出，〈K〉明显减小.讨论了〈K〉与晶粒尺寸D及初始磁导率的关系. 关键词： 纳米晶 有效磁各向异性 磁导率 FeCo基合金     

GaN MOS-HEMT Using Ultra-Thin A1203 Dielectric Grown by Atomic Layer Deposition

We report a GaN metal-oxide-semiconductor high electron mobility transistor （MOS-HEMT） with atomic layer deposited （ALD） Al2O3 gate dielectric. Based on the previous work [Appl. Phys. Lett. 86 （2005） 063501] of Ye et al. by decreasing the thickness of the gate oxide to 3.5nm and optimizing the device fabrication process, the device with maximum transconductance of 150mS/mm is produced and discussed in comparison with the result of lOOmS/mm of Ye et al. The corresponding drain current density in the 0.8-μm-gate-length MOS-HEMT is 800mA/mm at the gate bias of 3.0 V. The gate leakage is two orders of magnitude lower than that of the conventional A1GaN/GaN HEMT. The excellent characteristics of this novel MOS-HEMT device structure with ALD Al2O3 gate dielectric are presented.     

The Anomalous Effect of Interface Traps on Generation Current in Lightly Doped Drain nMOSFET＇s

The anomalous phenomenon of generation current ICD in the lightly doped drain （LDD） nMOSFET measured under the drain bias VD-step mode is reported. We propose an assumption of activated （A） and frozen （F） traps for the VD-step mode： The A traps contributes to ICD while the F process can make them lose the roles as generation centers. The A and F regions can form the F-A region. The comparison of the F and A regions decides the role of the F-A region. The experiments confirm the assumption.