CMOS vision sensor with integrated into low fully digital image process power 1/8-inch chip

A digital still camera image processing system on a chip, different from the video camera system, is pre- sented for mobile phone to reduce the power consumption and size. A new color interpolation algorithm is proposed to enhance the image quality. The system can also process fixed patten noise （FPN） reduction, color correction, gamma correction, RGB/YUV space transfer, etc. The chip is controlled by sensor regis- ters by inter-integrated circuit （I2C） interface. The voltage for both the front-end analog and the pad cir- cuits is 2.8 V, and the volatge for the image signal processing is 1.8 V. The chip running under the external 13.5-MHz clock has a video data rate of 30 frames/s and the measured power dissipation is about 75 roW.     

Enhanced NIR emission in Ce^3＋/Er^3＋-doped YAG induced by Bi^3＋ doping

Ce^3＋/Er^3＋/Bi^3＋ triply-doped yttrium aluminum garnet （YAG） is synthesized using co-precipitation method. The Bi^3＋ concentration-dependent near-infrared （NIR） emission behavior is systemically in- vestigated. The NIR emission of Er^3＋ ions at 1531 nm is enhanced threefold by the addition of 7 mol% Bi^3＋. Bi^3＋doping results in the formation of exciton in YAG and the variation in the local environment of the doped rare-earth ions. The enhancement in NIR luminescence is ascribed to the combined effects of the sensitization of exciton→Ce^3＋ →Er^3＋ and the Bi^3＋ doping-induced adjustment of the local environment for Ce^3＋ and Er^3＋ ions.     

New DDSCR structure with high holding voltage for robust ESD applications

A novel dual direction silicon-controlled rectifier(DDSCR)with an additional P-type doping and gate(APGDDSCR)is proposed and demonstrated.Compared with the conventional low-voltage trigger DDSCR(LVTDDSCR)that has positive and negative holding voltages of 13.371 V and 14.038 V,respectively,the new DDSCR has high positive and negative holding voltages of 18.781 V and 18.912 V in a single finger device,respectively,and it exhibits suitable enough positive and negative holding voltages of 14.60 V and 14.319 V in a four-finger device for±12-V application.The failure current of APGDDSCR is almost the same as that of LVT-DDSCR in the single finger device,and the four-finger APGDDSCR can achieve positive and negative human-body model(HBM)protection capabilities of 22.281 kV and 23.45 kV,respectively,under 40-V voltage of core circuit failure,benefitting from the additional structure.The new structure can generate a snapback voltage on gate A to increase the current gain of the parasitic PNP in holding voltage.Thus,a sufficiently high holding voltage increased by the structure can ensure that a multi-finger device can also reach a sufficient holding voltage,it is equivalent to solving the non-uniform triggering problem of multi-finger device.The operating mechanism and the gate voltage are both discussed and verified in two-dimensional(2D)simulation and experiemnt.     

A novel wide-dynamic-range logarithmic-response bipolar junction photogate transistor for CMOS imagers

In this paper, a new photodetector, bipolar junction photogate transistor (BJPG), is proposed for CMOS imagers. Due to an injection p+n junction introduced, the photo-charges drift through the p+n junction by the applied electronic field, and on the other hand, the p+n junction injects the carriers into the channel to carry the photo-charges. Therefore this device can increase the readout rate of the pixel signal charges and the photoelectron transferring efficiency. Using this new device, a new type of logarithmic pixel circuit is obtained with a wide dynamic range which makes photo-detector more suitable for imaging the naturally illuminated scenes. The simulations show that the photo current density of BJPG increases logarithmically with the incident light power due to the introduced injection p+n junction. The noise characteristics of BJPG are analyzed in detail and a new gate-induced noise is proposed. Based on the established numerical analytical model of noise, the power spectrum density curves a     

低过偏压下高增益单光子雪崩二极管的设计与验证

单光子雪崩二极管(SPAD)可以检测到异常微弱的光信号，可广泛应用于目标跟踪、自动驾驶、荧光检测等领域。本文基于180 nm标准双极-互补金属氧化物半导体-双扩散金属氧化物半导体(BCD)工艺，设计了一种低过偏压下具有高光子检测概率(PDP)的SPAD器件。该器件在440～740 nm范围内具有良好的光谱响应。采用半径为10μm的N+/P阱形成PN结作为感光区域，由N阱形成一个能有效防止边缘击穿的保护环。应用计算机技术辅助设计(TCAD)软件对SPAD的基本工作原理进行了定性分析，并通过建立的测试平台获得了设备的实际电气参数。测试结果表明，在1 V的过量偏置电压下，在480～660 nm的波长范围内，该器件可达到30%以上的PDP。在560 nm时，PDP峰值为42.7%，暗计数率为11.5 Hz/μm²。最后通过设计VerilogA混合模型验证了器件的模拟结果和实测结果之间具有良好一致性。     

一种改进型单光子雪崩二极管探测概率模型及验证

基于半导体工艺器件仿真软件和Matlab编程，对光子探测概率（PDP）进行了建模和实验表征。进一步考虑器件表面二氧化硅薄膜的光透射性，可以准确预测单光子雪崩二极管（SPAD）的性能。将模拟结果与采用0.18μm标准双极-互补金属氧化物半导体-双重扩散金属氧化物半导体（BCD）工艺设计和加工的SPAD的结果进行比较。结果显示，PDP的预测结果与实验结果之间具有良好的一致性，平均误差为1.72%。该模型可以减少商用器件仿真软件中存在的不收敛问题，极大减少了开发SPAD器件新结构所需的时间和成本。