用干涉方法研究超薄栅MOS系统中FN振荡电流

采用干涉方法研究FN振荡电流,得到一个精确而且简单的测量栅介质层的厚度及隧穿电子在栅介质层导带中的有效质量的表达式.通过和求解三角势垒的薛定谔方程得到的结果比较验证了干涉方法的可行性.干涉方法揭示电子在隧穿过程中体现了波的本性,这种方法的一个重要特征是它对不同形状的势垒和势阱可能均适用.还分析了有关FN振荡电流的实验现象,并给出了相应的物理解释.     

Evaluation of negative bias temperature instability in ultra-thin gate oxide pMOSFETs using a new on-line PDO method

A new on-line methodology is used to characterize the negative bias temperature instability (NBTI) without inherent recovery. Saturation drain voltage shift and mobility shift are extracted by I_D-V_D characterizations, which were measured before stress, and after every certain stress phase, using the proportional differential operator (PDO) method. The new on-line methodology avoids the mobility linearity assumption as compared with the previous on-the-fly method. It is found that both reaction--diffusion and charge-injection processes are important in NBTI effect under either DC or AC stress. A similar activation energy, 0.15 eV, occurred in both DC and AC NBTI processes. Also degradation rate factor is independent of temperature below 90\du\ and sharply increases above it. The frequency dependence of NBTI degradation shows that NBTI degradation is independent of frequencies. The carrier tunnelling and reaction--diffusion mechanisms exist simultaneously in NBTI degradation of sub-micron pMOSFETs, and the carrier tunnelling dominates the earlier NBTI stage and the reaction--diffusion mechanism follows when the generation rate of traps caused by carrier tunnelling reaches its maximum.     

The conduction mechanism of stress induced leakage current through ultra-thin gate oxide under constant voltage stresses

The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.     

Effect of Reverse Substrate Bias on Degradation of Ultra-Thin Gate-Oxide n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors under Different Stress Modes

Degradation of ultra-thin gate-oxide n-channel metal-oxide-semiconductor field-effect transistors with the halo structure has been studied under different stress modes with a reverse substrate bias. The device degradation under the same stress mode with different reverse substrate voltages has been characterized by monitoring the substrate current in a stressing process, which follows a simple power law. When the gate voltage is less than the critical value, the device degradation will first decrease and then increase with the increasing reverse substrate voltage, otherwise, the device degradation will increase continuously. The critical value can be obtained by measuring the substrate current variation with the increases of reverse substrate voltage and gate voltage. The experimental results indicate that the stress mode with enhanced injection efficiency and smaller device degradation can be obtained when the gate voltage is less than the critical value with a proper reverse substrate voltage chosen.     

超薄栅氧化层n-MOSFET软击穿后的导电机制

研究了恒压应力下超薄栅氧化层n型金属-氧化物-半导体场效应晶体管（n-MOSFET）软击穿 后的导电机制.发现在一定的栅电压V_g范围内，软击穿后的栅电流I_g符合Fowl er-Nordheim隧穿公式，但室温下隧穿势垒_b的平均值仅为0936eV，远小于S i/Si O₂界面的势垒高度315eV.研究表明，软击穿后，处于Si/SiO₂界 面量子化能级上的 电子不隧穿到氧化层的导带，而是隧穿到氧化层内的缺陷带上._b与缺陷带能 级和电 子所处的量子能级相关；高温下，激发态电子对隧穿电流贡献的增大导致_b逐 渐降低. 关键词： 软击穿 栅电流 类Fowler-Nordheim隧穿 超薄栅氧化层     

用干涉方法研究超薄栅MOS系统中的FN振荡电流

采用干涉方法研究ＦＮ振荡电流，得到一个精确而且简单的测量栅介质层的厚度及隧穿电子在栅介质层导带中的有效质量的表达式。通过和求解三角势垒的薛定谔方程得到的结果比较验证了干涉方法的可行性。干涉方法揭示电子在隧穿过程中体现了波的本性，这种方法的一个重要特征是它对不同形状的势垒和势阱可能均适用。还分析了有关ＦＮ振荡电流的实验现象，并给出了相应的物理解释。     

Low voltage substrate current： a monitor for interface states generation in ultra-thin oxide n-MOSFETs under constant voltage stresses

The low voltage substrate current （Ib） has been studied based on generation kinetics and used as a monitor of interface states （Nit） generation for ultra-thin oxide n-MOSFETs under constant voltage stress. It is found that the low voltage Ib is formed by electrons tunnelling through interface states, and the variations of Ib（△Ib） are proportional to variations of Nit （△Nit）. The Nit energy distributions were determined by differentiating Nit（Vg）. The results have been compared with that measured by using gate diode technique.[第一段]