Improved high-frequency equivalent circuit model based on distributed effects for SiGe HBTs with CBE layout

In this paper, we present an improved high-frequency equivalent circuit for SiGe heterojunction bipolar transistors(HBTs) with a CBE layout, where we consider the distributed effects along the base region. The actual device structure is divided into three parts: a link base region under a spacer oxide, an intrinsic transistor region under the emitter window,and an extrinsic base region. Each region is considered as a two-port network, and is composed of a distributed resistance and capacitance. We solve the admittance parameters by solving the transmission-line equation. Then, we obtain the smallsignal equivalent circuit depending on the reasonable approximations. Unlike previous compact models, in our proposed model, we introduce an additional internal base node, and the intrinsic base resistance is shifted into this internal base node,which can theoretically explain the anomalous change in the intrinsic bias-dependent collector resistance in the conventional compact model.     

Analytical capacitance model for 14 nm Fin FET considering dual-k spacer

The conformal mapping of an electric field has been employed to develop an accurate parasitic capacitance model for nanoscale fin field-effect transistor(Fin FET) device. Firstly, the structure of the dual-layer spacers and the gate parasitic capacitors are thoroughly analyzed. Then, the Cartesian coordinate is transferred into the elliptic coordinate and the equivalent fringe capacitance model can be built-up by some arithmetical operations. In order to validate our proposed model, the comparison of statistical analysis between the proposed calculation and the 3D-TCAD simulation has been carried out, and several different material combinations of the dual-k structure have been considered. The results show that the proposed analytical model can accurately calculate the fringe capacitance of the Fin FET device with dual-k spacers.     

Detailed study of NBTI characterization in 40-nm CMOS process using comprehensive models

The impact of negative bias temperature instability(NBTI) can be ascribed to three mutually uncorrelated factors, including hole trapping by pre-existing traps(?V_(HT)) in gate insulator, generated traps(?V_(OT)) in bulk insulator, and interface trap generation(?V_(IT)). In this paper, we have experimentally investigated the NBTI characteristic for a 40-nm complementary metal–oxide semiconductor(CMOS) process. The power-law time dependence, temperature activation, and field acceleration have also been explored based on the physical reaction–diffusion model. Moreover, the end-of-life of stressed device dependent on the variation of stress field and temperature have been evaluated. With the consideration of locking effect, the recovery characteristics have been modelled and discussed.