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Fabrication and characterization of groove-gate MOSFETs based on a self-aligned CMOS process 总被引:2,自引:0,他引:2 下载免费PDF全文
N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process
have been fabricated and characterized. For the devices with channel length
of 140nm, the measured drain induced barrier lowering (DIBL) was 66mV/V for
n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate
n-MOSFET was 150 times less than that of a conventional planar n-MOSFET.
These results demonstrate that groove-gate MOSFETs have excellent
capabilities in suppressing short-channel effects. It is worth emphasizing
that our groove-gate MOSFET devices are fabricated by using a simple process
flow, with the potential of fabricating devices in the sub-100nm range. 相似文献
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