控制氧化层对双势垒纳米硅浮栅存储结构性能的影响

在等离子体增强化学气相沉积(PECVD)系统中,利用逐层淀积非晶硅(a-Si)和等离子体氧化相结合的方法制备二氧化硅(SiO₂)介质层.电容电压(C-V)和电导电压(G-V)测量结果表明：利用该方法在低温(250 ℃)条件下制备的SiO₂介质层均匀致密,其固定氧化物电荷和界面态密度分别为9×10¹¹cm^-2和2×10¹¹cm^-2·eV^-1,击穿场强达4.6 MV/cm,与热氧化形成的SiO₂介质层的性质相当.将该SiO₂介质层作为控制氧化层应用在双势垒纳米硅(nc-Si)浮栅存储结构中,通过调节控制氧化层的厚度,有效阻止栅电极与nc-Si之间的电荷交换,延长存储时间,使存储性能得到明显改善. 关键词： 等离子体氧化 二氧化硅 纳米硅 控制氧化层     

Large Storage Window in a-SiNx/nc-Si/a-SiNx Sandwiched Structure for Nanocrystalline Silicon Floating Gate Memory Application

An a-SiNx/nanocrystalline silicon [（nc-Si）/a-SiNx] sandwiched structure is fabricated in a plasma enhanced chemical vapour deposition （PECVD） system at low temperature （250℃）. The nc-Si layer is fabricated from a hydrogen-diluted silane mixture gas by using a layer-by-layer deposition technique. Atom force microscopy measurement shows that the density of nc-Si is about 2 ×10^11 cm^-2. By the pretreatment of plasma nitridation, low density of interface states and high-quality interface between the Si substrate and a-SiNs insulator layer are obtained. The density of interface state at the midgap is calculated to be 1 ×10^10 cm^-2eV^-1 from the quasistatic and high frequency C - V data. The charging and discharging property of nc-Si quantum dots is studied by capacitance-voltage （C- V） measurement at room temperature. An ultra-large hysteresis is observed in the C - V characteristics, which is attributed to storage of the electrons and holes into the nc-Si dots. The long-term charge-loss process is studied and ascribed to low density of interface states at SiNx/Si substrate.     

量子点浮置栅量子线沟道三栅结构单电子场效应管存储特性的数值模拟

通过建立二维薛定谔方程和泊松方程数值模型,对基于硅量子点浮置栅和硅量子线沟道三栅结构单电子场效应管(FET)存储特性进行了研究.通过在不同尺寸、栅压和不同写入电荷条件下,对硅量子线沟道中电子浓度的二维有限元自洽数值求解,研究了在纳米尺度下硅量子线沟道中量子限制效应和电荷分布对于器件特性的影响.模拟结果发现,沟道的导通阈值电压随着尺寸的缩小而提高,并随浮置栅内存储的电子数目的增加而明显升高.然而,这样的增加趋势在受到纳米尺度沟道中高电荷密度的影响下将出现非线性饱和趋势.进一步研究发现,当沟道尺寸较小时,沟道 关键词： 三栅单电子FET存储器 量子效应 薛定谔方程 泊松方程     

氮化硅介质中双层纳米硅薄膜的两级电荷存储

研究镶嵌在超薄非晶氮化硅(a-SiN_x)层之间的双层纳米硅(nc-Si)的电荷存储现象.利用等离子体增强化学气相淀积(PECVD)技术在硅衬底上制备a-SiN_x/a-Si/a-SiN_x/a-Si/a-SiN_x多层薄膜结构.采用常规热退火方法使非晶硅(a-Si)层晶化，形成包含双层nc-Si的金属-氮化物-半导体(MIS)结构.通过电容电压(C-V)特性测量，观测到该结构中由于电荷存储引起的C-V回滞现象，并在室温下成功观察到载流子基于Fowler-Nordheim(F-N)隧穿注入到第一层、第二层nc-Si的两级电荷存储状态.结合电流电压(I-V)特性的测量，对电荷存储的机理进行了深入分析. 关键词： 纳米硅 氮化硅 电容电压法 电流电压法     

Electronic Properties of Nanocrystalline-Si Embedded in Asymmetric Ultrathin SiO2 by In-Situ Fabrication Technique

Structures of nanocrystalline-Si (nc-Si) sandwiched between two asymmetric ultrathin SiO2 layers were fabricated. The nc-Si (dot density of 10^11 cm^-2) was formed by decomposition of hydrogen-diluted silane and the ultrathin SiO2 layers (about 2 nm) were prepared by plasma oxidation at a lower temperature (250℃). The whole fabrication processes were completed in situ in a plasma-enhanced chemical vapour deposition system. By using the capacitance-voltage ( C-V) and conductance-voltage ( G-V) spectroscopy, we studied the electronic properties of the annealed samples. The experimental results show that there are distinct capacitance peaks and conductance plateau or peaks for annealed samples at room temperature, which can be explained by direct tunnelling of electrons into the nc-Si. At the same time, Coulomb blockade plays an important role in the electronic transport in the nc-Si. The effect of thermal annealing in N2 ambient on the electronic properties was studied and the results indicate that high temperature (1000℃) annealing can improve the size uniformity of the nc-Si prepared by decomposition of hydrogen-diluted silane.