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随着深度学习的高速发展,目前智能算法的飞速更新迭代对硬件算力提出了很高的要求.受限于摩尔定律的告竭以及冯·诺伊曼瓶颈,传统CMOS集成无法满足硬件算力提升的迫切需求.利用新型器件忆阻器构建神经形态计算系统可以实现存算一体,拥有极高的并行度和超低功耗的特点,被认为是解决传统计算机架构瓶颈的有效途径,受到了全世界的广泛关注.本文按照自下而上的顺序,首先综述了主流忆阻器的器件结构、物理机理,并比较分析了它们的性能特性.然后,介绍了近年来忆阻器实现人工神经元和人工突触的进展,包括具体的电路形式和神经形态功能的模拟.接着,综述了无源和有源忆阻阵列的结构形式以及它们在神经形态计算中的应用,具体包括基于神经网络的手写数字和人脸识别等.最后总结了目前忆阻类脑计算从底层到顶层所遇到的挑战,并对该领域后续的发展进行了展望. 相似文献
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In this work, we investigate strain effects induced by the
deposition of gate dielectrics on the valence band structures in Si
(110) nanowire via the simulation of strain distribution and the
calculation of a generalized 6 × 6k$\cdot$p strained
valence band. The nanowire is surrounded by the gate dielectric. Our
simulation indicates that the strain of the amorphous SiO2 insulator is negligible without considering temperature factors. On
the other hand, the thermal residual strain in a nanowire with
amorphous SiO2 insulator which has negligible lattice misfit
strain pushes the valence subbands upwards by chemical vapour
deposition and downwards by thermal oxidation treatment. In contrast
with the strain of the amorphous SiO2 insulator, the strain of
the HfO2 gate insulator in Si (110) nanowire pushes the valence
subbands upwards remarkably. The thermal residual strain by
HfO2 insulator contributes to the up-shifting tendency. Our
simulation results for valence band shifting and warping in Si
nanowires can provide useful guidance for further nanowire device
design. 相似文献
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