SiC电子霍耳迁移率的计算

基于对自身能带结构的分析以及各向同性弛豫时间近似法,采用三椭球等能面、抛物线性简化,建立了适于模拟n型6H-SiC电子霍耳迁移率和霍耳散射因子的解析模型,精确描述了不同散射机制对于6H-SiC低场电子输运特性的影响.计算结果与实测值有很好的一致性.     

超导Josephson结直流Ⅰ-Ⅴ特性的数值计算

为了研究超导Josephson结的性质,选用四阶龙格-库塔法对RSJ模型下单个Josephson结及其阵列以及微波辐照下Josephson结的直流Ⅰ-Ⅴ特性进行了数值计算,并将模拟结果与实验结果进行了比较.     

具有部分本征GaN帽层新型AlGaN/GaN高电子迁移率晶体管特性分析

为了优化传统Al GaN/GaN高电子迁移率晶体管(high electron mobility transistors,HEMTs)器件的表面电场,提高击穿电压,本文提出了一种具有部分本征GaN帽层的新型Al GaN/GaN HEMTs器件结构.新型结构通过在Al GaN势垒层顶部、栅电极到漏电极的漂移区之间引入部分本征GaN帽层,由于本征GaN帽层和Al GaN势垒层界面处的极化效应,降低了沟道二维电子气(two dimensional electron gas,2DEG)的浓度,形成了栅边缘低浓度2DEG区域,使得沟道2DEG浓度分区,由均匀分布变为阶梯分布.通过调制沟道2DEG的浓度分布,从而调制了Al GaN/GaN HEMTs器件的表面电场.利用电场调制效应,产生了新的电场峰,且有效降低了栅边缘的高峰电场,Al GaN/GaN HEMTs器件的表面电场分布更加均匀.利用ISE-TCAD软件仿真分析得出:通过设计一定厚度和长度的本征GaN帽层,Al GaN/GaN HEMTs器件的击穿电压从传统结构的427 V提高到新型结构的960 V.由于沟道2DEG浓度减小,沟道电阻增加,使得新型Al GaN/GaN HEMTs器件的最大输出电流减小了9.2%,截止频率几乎保持不变,而最大振荡频率提高了12%.     

β-SiC薄膜在SF6和SF6+O2中的等离子体刻蚀研究

以SF₆和SF₆+O₂为刻蚀气体,采用等离子体刻蚀工艺成功地对化学气相淀积工艺制备的β-SiC单晶薄膜进行了有效的刻蚀去除.实验指出当气体混合比约为40%时,刻蚀速率达到最大值.俄歇能谱分析表明,在SF₆和SF₆+O₂气体中被刻蚀后的样品没有形成富C表面的SiC层.研究结果为各种SiC器件的研制奠定了必要的实验基础. 关键词：     

硅基单片式复合晶体管的结构参数对高功率微波损伤效应的影响（英文）

建立了三种不同结构的硅基单片式复合晶体管(由T1和T2两个晶体管构成)的二维电热模型,研究了高功率微波对不同结构的硅基单片式复合晶体管的损伤效应的影响。获得了不同器件结构下导致复合晶体管损伤的损伤功率阈值和损伤能量阈值分别与脉宽的关系。结果表明,当复合晶体管的总体尺寸不变而T2和T1晶体管的面积比值更大时需要更多的功率和能量来损伤器件。通过分析器件内部电场、电流密度和温度分布的变化,得到了复合晶体管的结构对其微波损伤效应的影响规律。对比发现,三种结构的复合晶体管的损伤点均位于T2管的发射极附近,随着T2和T1晶体管面积比的增大,电场、电流密度和温度在器件内部的分布将变得更加分散。此外,在发射极处增加外接电阻Re,研究表明损伤时间随发射极电阻的增大而增加。因此可以得出结论,适当改变器件结构或增加外接元件可以增强器件的抗微波损伤能力。晶体管的仿真毁伤点与实验结果一致。     

考虑通孔效应和边缘传热效应的纳米级互连线温度分布模型

提出了同时考虑通孔效应和边缘传热效应的互连线温度分布模型,获得了适用于单层互连线和多层互连线温度分布的解析模型,并基于65 nm互补金属氧化物半导体（CMOS）工艺参数计算了不同长度单层互连线和多层互连线的温度分布.对于单层互连线,考虑通孔效应后中低层互连线的温升非常低,而全局互连线几乎不受通孔效应的影响,温升仍然很高.对于多层互连线,最上层互连线的温升最高,温升和互连介质层厚度近似成正比,而且互连介质材料热导率越低,温升越高.所提出的互连线温度分布模型,能应用于纳米级CMOS计算机辅助设计. 关键词： 通孔效应 边缘传热效应 纳米级互连线 温度分布模型     

Pulsed microwave damage trend of bipolar transistor as a function of pulse parameters

In the present paper we conduct a theoretical study of the thermal accumulation effect of a typical bipolar transistor caused by high power pulsed microwave (HPM), and investigate the thermal accumulation effect as a function of pulse repetition frequency (PRF) and duty cycle. A study of the damage mechanism of the device is carried out from the variation analysis of the distribution of the electric field and the current density. The result shows that the accumulation temperature increases with PRF increasing and the threshold for the transistor is about 2 kHz. The response of the peak temperature induced by the injected single pulses indicates that the falling time is much longer than the rising time. Adopting the fitting method, the relationship between the peak temperature and the time during the rising edge and that between the peak temperature and the time during the falling edge are obtained. Moreover, the accumulation temperature decreases with duty cycle increasing for a certain mean power.     

考虑自热效应的互连线功耗优化模型

基于互连线的分布式功耗模型,考虑自热效应的同时采用非均匀互连线结构,提出了一种基于延时、带宽、面积、最小线宽和最小线间距约束的互连动态功耗优化模型.分别在90和65 nm互补金属氧化物半导体工艺节点下验证了功耗优化模型的有效性,在工艺约束下同时不牺牲延时、带宽和面积所提模型能够降低高达35％互连线功耗.该模型适用于片上网络构架中大型互连路由结构和时钟网络优化设计.     

Fast-switching SOI-LIGBT with compound dielectric buried layer and assistant-depletion trench

A lateral insulated gate bipolar transistor (LIGBT) based on silicon-on-insulator (SOI) structure is proposed and investigated. This device features a compound dielectric buried layer (CDBL) and an assistant-depletion trench (ADT). The CDBL is employed to introduce two high electric field peaks that optimize the electric field distributions and that, under the same breakdown voltage (BV) condition, allow the CDBL to acquire a drift region of shorter length and a smaller number of stored carriers. Reducing their numbers helps in fast-switching. Furthermore, the ADT contributes to the rapid extraction of the stored carriers from the drift region as well as the formation of an additional heat-flow channel. The simulation results show that the BV of the proposed LIGBT is increased by 113% compared with the conventional SOI LIGBT of the same length L_D. Contrastingly, the length of the drift region of the proposed device (11.2 μ) is about one third that of a traditional device (33 μ) with the same BV of 141 V. Therefore, the turn-off loss (E_OFF) of the CDBL SOI LIGBT is decreased by 88.7% compared with a conventional SOI LIGBT when the forward voltage drop (V_F) is 1.64 V. Moreover, the short-circuit failure time of the proposed device is 45% longer than that of the conventional SOI LIGBT. Therefor, the proposed CDBL SOI LIGBT exhibits a better V_F-E_OFF tradeoff and an improved short-circuit robustness.     

一种基于多目标约束的互连线宽和线间距优化模型

优化线宽和线间距已经成为改善系统芯片性能的关键技术.本文基于互连线线宽和线间距对互连延时、功耗、面积和带宽的影响,提出了基于多目标优化方法实现优化线宽和线间距的思路,并利用曲线拟合方法得到了多目标约束的解析模型.Hspice验证结果显示,该解析模型精度较高,平均误差不超过5%,算法简单,能有效弥补应用品质因数方法的缺陷,可以应用于纳米级互补金属氧化物半导体系统芯片的计算机辅助设计.