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Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits.Based on the RLC interconnect delay model,by wire sizing,wire spacing and adopting low-swing interconnect technology,this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously.The optimized model is verified based on 65-nm and 90-nm complementary metal-oxide semiconductor(CMOS) interconnect parameters.The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process.The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip. 相似文献
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应用断流分光光度计(Stopped-Flow Spectrophotometer)研究了镍(II)与N-(对位取代苯基)氨基乙酸-(ρ-RC6H4NHCH2COOH, R=CH3O, CH3, H, Cl, 简写为NROH或HL)在25℃及30%(v/v)乙醇溶液中生成配合物的反应动力学. 实验结果表明, 不仅氨基酸配体的负离子(NRO^-或L^-)具有较高的反应活性, 而且两性离子(HN^+RO^-或^+HL^-)也是有效的反应配体. 反应按双途径进行, 即按Eigen-Tamm机理进行的NRO^-途径和以质子迁移为速率控制步骤的两性离子途径. 两性离子的反应活性(以log kHL^±表示)与配体的碱性强度(pK2)之间呈现直线自由能关系. 并发现镍(II)配合物的离解反应速率常数(log k-L^-)与配体的碱性强度(pK2)和配合物的稳定常数(log KNiL^N^i)之间均存在直线自由能关系. 相似文献
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Parasitic effects of air-gap through-silicon vias in high-speed three-dimensional integrated circuits 下载免费PDF全文
In this paper,ground-signal-ground type through-silicon vias(TSVs) exploiting air gaps as insulation layers are designed,analyzed and simulated for applications in millimeter wave.The compact wideband equivalent-circuit model and passive elements(RLGC) parameters based on the physical parameters are presented with the frequency up to 100 GHz.The parasitic capacitance of TSVs can be approximated as the dielectric capacitance of air gaps when the thickness of air gaps is greater than 0.75 μm.Therefore,the applied voltage of TSVs only needs to achieve the flatband voltage,and there is no need to indicate the threshold voltage.This is due to the small permittivity of air gaps.The proposed model shows good agreement with the simulation results of ADS and Ansoft's HFSS over a wide frequency range. 相似文献
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The kinetics of the metal exchange reactions between (5-R-phen)copper(II) (R = Me, H, Cl, and NO2) and Ni(II) was studied at 25?and ionic strength 1.0 mol dm-3 or pH 2.3-3.5. The rate of the exchange reactions was measured by a spectrophotometer. The reactions appeared to proceed through 3 different pathways which involved H+ attack and Ni attack as well as a pH- and Ni-independent dissociation of the complexes. The kinetics conforms to the following rate law: d[Ni(5-R-phen)]/dt = (kp + kH[H+] + kNi[Ni2+])[(Cu(5-R-phen)2+]. The reaction rate of the 3 pathways increased with decreasing basicity of the ligand. Some linear free energy relationships were found to exist between the reactivity of these Cu(II) complexes and the base strength of the ligand 5-R-phen. The mechanisms of the reactions are discussed. 相似文献
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具有共轭主链聚合物单晶的低温电导测定 总被引:2,自引:0,他引:2
用自行组装的低温电导测定装置对77~373K温度范围内双(对甲苯磺酸)-2,4-己二炔-1,6-二醇酯(TS)及其聚合物PTS单晶体的暗电导进行了测定。在c方向上相应于它们低温相转变的温度,TS和PTS的电导均出现异常,此时TS的相变温度是163K和208K。 相似文献
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An interconnecting bus power optimization method combining interconnect wire spacing with wire ordering 下载免费PDF全文
On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses. 相似文献