Automation of a Mass Flow Controller for Application in Time‐Multiplex SF6+CH4 Plasma Etching of Silicon

In this work is proposed the automation of a gas injection (mass flow) system in order to generate timemultiplex SF₆/CH₄ radiofrequency plasma applied for silicon (Si) etching process. The control of the gas injection system is important in order to better control the process anisotropy, i.e., the high‐aspect‐ratio of mask pattern transfer to substrate surface. In other words, this control allows the attainment of deep Si etching process. Here, the automation of the gas injection system was realized through the interface between a computer and a data acquisition board. The automation software developed allows controlling the gas flow rate switching it on and off during whole process through the use of a square waveform routine, intermittent flow, beyond the conventional condition of a fixed value for gas flow rate, continuous flow. In order to investigate the time‐multiplex SF₆/CH₄ plasma etching of Si, the residual gas analysis was performed. The investigations were made keeping the following process parameters: flow of SF₆: 10 sccm, flow of CH₄: 6 sccm, 100 W rf power, wave period: 20 sec. It were monitored the partial pressure of SF⁺ ₅ (parent neutral specie: SF₆), CH⁺₄ (CH4) and SiF+ ₃ (SiF4) species as a function of time for different gas flow switching and duty cycle. The results showed that with the generation of plasma occurs a drastic change in behavior of partial pressures of SF⁺ ₅ and CH⁺₄ species. Moreover, it is evidenced that the interactions between the SF₆ and CH₄ fragments promotes a high production rate of HF molecule and consequently a decrease of atomic fluorine, mainly when plasma is on. Finally, the behavior of partial pressure of SiF⁺ ₃ specie for alternatively intermittent SF₆ and CH₄ flow operation shows us that both the etching processes and the deposition of a polymer passivation layer are occurring alternatively, a desirable feature for multi‐step etching process (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

分步法高速沉积微晶硅薄膜

为提高微晶硅薄膜的纵向结晶性能, 在甚高频等离子体增强化学气相沉积技术的基础上, 采用过渡参数缓变和两步法相结合的方法在普通玻璃衬底上高速沉积薄膜. 当功率密度为2.1 W/cm², 硅烷浓度在6%和9.6%之间变化时, 从薄膜方向和玻璃方向测算的Raman晶化率的差异维持在2%以内. 硅烷浓度为9.6%时, 薄膜沉积速率可达3.43 nm/s, 从薄膜方向和玻璃方向测算的Raman晶化率分别为50%和48%, 差异的相对值仅为4.0%. 合理控制过渡阶段的参数变化, 可使两个方向的Raman晶化率差值下降到一个百分点. 表明采用新方法制备薄膜, 不仅可以抑制非晶孵化层的形成, 改善微晶硅薄膜的纵向结构, 还为制备优质薄膜提供了较宽的参数变化空间. 关键词： 微晶硅薄膜 非晶孵化层 高速沉积 甚高频等离子体增强化学气相沉积     

梯形截面硅基水平多槽纳米线定向耦合器全矢量分析

定向耦合器是构成各类光子器件的基础元件. 本文采用一种基于电场分量的全矢量有限元法, 分析由梯形截面硅基水平多槽纳米线构成的定向耦合器. 给出了准TE与准TM偶、奇模有效折射率、耦合长度及模场分布, 揭示了其模式的混合特性及模场分布特点. 分析结果表明, 准TE模与准TM模的耦合长度随波导间距的增大均呈指数增长, 其中准TE模的耦合长度对波导侧壁倾角的变化敏感, 而准TM模的耦合长度对槽厚及槽折射率的变化敏感. 恰当选择结构与材料参数, 可实现两偏振态下相同耦合长度, 定向耦合器在偏振无关条件下工作.     

热处理对富硅氧化硅薄膜中硅纳米晶形成的影响

采用磁控溅射法制备了富硅氧化硅薄膜, 然后分别经过一步热处理、两步热处理和快速热处理制备了镶嵌有硅纳米晶的氧化硅薄膜. 实验结果表明, 在硅含量为～ 42.63 at.%的富硅氧化硅薄膜中, 三种热处理均能形成10¹²/cm²量级的硅纳米晶. 其中在两步热处理中, 硅纳米晶的密度最高, 达到2.2× 10¹²/cm², 并且尺寸均匀、结晶完整性好; 一步热处理后的样品中, 硅纳米晶密度较低, 并且部分纳米晶结晶不充分; 快速热处理后的样品中, 硅纳米晶密度最低、尺寸分布不均匀, 并且存在孪晶结构. 分析认为, 热处理初始阶段的形核过程对纳米晶的密度及微观结构有着重要的影响, 两步热处理中的低温段促进了纳米晶的成核, 有助于形成高密度高质量硅纳米晶.     

Al2O3钝化及其在晶硅太阳电池中的应用

介绍了Al₂O₃的材料性质及其原子层沉积制备方法, 详细阐述了该材料的钝化机制(化学钝化和场效应钝化), 并从薄膜厚度、热稳定性及叠层钝化等角度阐释其优化方案. 概述了Al₂O₃钝化在晶体硅太阳电池中的应用, 主要包括钝化发射极及背面局部扩散电池和钝化发射极及背表面电池. 最后, 对Al₂O₃钝化工艺的未来研究方向和大规模的工业应用进行了展望.     

点缺陷对硼掺杂直拉硅单晶p/p~+外延片中铜沉淀的影响

系统研究了点缺陷对晶体硅中氧沉淀生成的影响,及点缺陷和氧沉淀对重掺硼直拉硅单晶p/p⁺外延片中铜沉淀的影响.样品先在不同的气氛下进行1250℃/60 s快速热处理,随后在750℃/8 h+1050℃/16 h常规热处理过程中引入铜沾污.通过腐蚀结合光学显微镜研究发现,以O₂作为保护气氛时,p⁺衬底中的沉淀密度较小,以Ar和N₂作为保护气氛时,重掺硼p⁺衬底中生成了高密度的沉淀,且在上述所有样品的外延层中均无缺陷生成.研究认为,以O₂作为保护气时引入的自间隙硅原子（Si_I）可以抑制沉淀的形成,而以Ar和N₂作为保护气氛时引入的空位则会促进沉淀的生成,这是导致此差异的主要原因.另外,研究还发现,p/p⁺外延结构能很好地吸除硅片中的铜杂质,从而保持了外延层的洁净.     

一维衍射光栅和一维光子晶体组成的硅薄膜太阳能电池背反射器

设计了一种由一维衍射光栅和一维光子晶体组成的用于薄膜硅太阳能电池的背反射器,采用勒让德多项式展开法对一维光子晶体和三角形光栅结构进行了参数优化,并对400~1 200 nm入射电磁波的反射率进行了模拟计算。结果表明:在高反射率的一维光子晶体作用下,利用衍射光栅可以得到大倾角的反射光,有效地延长光子在电池吸收体的传播路径,使其得到充分吸收。衍射光栅加光子晶体结构的背反射器可以大幅提高电池的捕光能力,提高太阳能电池的转化效率。     

氢稀释对纳米晶硅薄膜晶化特性的影响及薄膜生长机理

以SiH4与H2作为前驱气体,采用射频等离子增强化学气相沉积技术制备了纳米晶硅薄膜.利用Raman散射和红外吸收光谱等技术,对不同氢稀释比条件下薄膜的微观结构和键合特性进行了研究.结果表明,随着氢稀释比增加,薄膜的晶化率明显提高,而氢稀释比过高时,薄膜晶化率呈现减少趋势.红外吸收光谱分析表明,纳米晶硅薄膜中氢的键合模式与薄膜的晶化特性密切相关.随着氢稀释比增加,薄膜中整体氢含量和SiH2键合密度明显减少,而在高氢稀释比条件下,氢稀释比增加导致薄膜中SiH2键合密度和整体氢含量增加.     

Electrical and optical characteristics of porous silicon impregnated with LaF3 by a novel chemical bath technique

The structural, electrical and optical characteristics of porous silicon (PS) due to the impregnation of LaF₃ into PS by a novel chemical-bath deposition (CBD) technique have been investigated in this article. Without removing the PS from the anodization chamber the impregnation with LaF₃ has been done by reacting LaCl₃ with HF in the same chamber at room temperature. The impregnation of LaF₃ was confirmed by the SEM on the cross-section of the LaF₃/PS/Si system and EDX. The modification of PS surface by LaF₃ had direct influence on the electrical and optical properties of PS. Electrical properties of Ag/LaF₃/PS/p-Si/Ag structures were studied through the current-voltage (I-V) and capacitance-voltage (C-V) characteristics. Formation of metal-insulator-semiconductor (MIS) diode was evident whose forward current increased with annealing. A diode factor of about 2.4 has been obtained for the annealed heterostructure indicating a high density of trap states. The C⁻²-V curves of all samples showed negative flat band voltage of around −2 V confirming a large number of fixed positive charges in the LaF₃. The photoluminescence (PL) intensity of the LaF₃-impregnated PS showed aging for the as-deposited samples, but when annealed PS structure recovered the PL intensity. Experimental results show that the optimized chemical bath passivation process for the LaF₃ on porous silicon could enable the porous silicon to be an important material for photonic application.     

Analysis of the breakdown mechanism for an ultra high voltage high-side thin layer silicon-on-insulator p-channel lateral double-diffused metal\ben oxide semiconductor

This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage (BV) for an ultra-high-voltage (UHV) high-side thin layer silicon-on-insulator (SOI) p-channel low-density metal-oxide semiconductor (LDMOS). Compared with the conventional simulation method, the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit. The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method. Simulation results show that the off-state (on-state) BV of the SOI p-channel LDMOS can reach 741 (620) V in the 3-μm-thick buried oxide layer, 50-μm-length drift region, and at -400 V back-gate voltage, enabling the device to be used in a 400 V UHV integrated circuit.