一种高精度低功耗流水线ADC开关电容电路

提出一种新的电容失配校正方案及功耗驱动的OTA设计思路,通过对虚地电容的修正,将电容失配因子在取样保持系统中去除,达到提高电容匹配程度,降低OTA增益误差的要求,使开关电容部分的瞬态功耗下降.本文采用TSMC 0.18μm工艺设计了一个8位,取样速率为200MHz的流水线结构模数转换器作为验证电路,仿真结果说明此优化结构符合高精度和低功耗要求,可应用到流水线等高速模数转换电路中作为信号前端处理模块使用.     

软件无线电的关键技术

软件无线电技术(Software Radio Technology)是近些年来发展起来的一种实现无线电通信的新兴技术，它是利用软件来实现无线通信系统的各种功能．本文介绍了软件无线电的概念和体系结构，详细分析了其实现的关键技术和难点。     

一种基于低待机功耗的彩电电源改进方案

从节能的角度出发，采用开关控制电路对传统彩电的调谐电压形成电路、视放电压形成电路以及消磁电路做了改进，可有效地降低彩电的待机功耗。     

基于C8051F的多通道模数转换系统的设计与应用

以Silicon Labs公司研发设计的C8051F020芯片为核心,详细剖析了该芯片的12位SAR ADC0模数转换模块,并在Keil uVision4和visual c++6.0环境中实现了仿真模拟.为了在仿真系统中更清晰明了地展现仿真结果,本系统使用UART接口,将仿真结果传输到上位机进行显示.     

Successive approximation-like 4-bit full-optical analog-to-digital converter based on Kerr-like nonlinear photonic crystal ring resonators

Implementing of photonic sampling and quantizing analog-to-digital converters (ADCs) enable us to extract a single binary word from optical signals without need for extra electronic assisting parts. This would enormously increase the sampling and quantizing time as well as decreasing the consumed power. To this end, based on the concept of successive approximation method, a 4-bit full-optical ADC that operates using the intensity-dependent Kerr-like nonlinearity in a two dimensional photonic crystal (2DPhC) platform is proposed. The Silicon (Si) nanocrystal is chosen because of the suitable nonlinear material characteristic. An optical limiter is used for the clamping and quantization of each successive levels that represent the ADC bits. In the proposal, an energy efficient optical ADC circuit is implemented by controlling the system parameters such as ring-to-waveguide coupling coefficients, the ring’s nonlinear refractive index, and the ring’s length. The performance of the ADC structure is verified by the simulation using finite difference time domain (FDTD) method.     

Integration of quantitative DCE-MRI and ADC mapping to monitor treatment response in human breast cancer: initial results

PURPOSE: The objective of this study was to assess changes in the water apparent diffusion coefficient (ADC) and in pharmacokinetic parameters obtained from the fast-exchange regime (FXR) modeling of dynamic contrast-enhanced magnetic resonance imaging (DCE-MRI) during neoadjuvant chemotherapy in breast cancer. MATERIALS AND METHODS: Eleven patients with locally advanced breast cancer underwent MRI examination prior to and after chemotherapy but prior to surgery. A 1.5-T scanner was used to obtain T1, ADC and DCE-MRI data. DCE-MRI data were analyzed by the FXR model returning estimates of K(trans) (volume transfer constant), v(e) (extravascular extracellular volume fraction) and tau(i) (average intracellular water lifetime). Histogram and correlation analyses assessed parameter changes post-treatment. RESULTS: Significant (P < .05) changes or trends towards significance (P < .10) were seen in all parameters except tau(i), although there was qualitative reduction in tau(i) values post-treatment. In particular, there was reduction (P < .035) in voxels with K(trans) values in the range 0.2-0.5 min(-1) and a decrease (P < .05) in voxels with ADC values in the range 0.99 x 10(-3) to 1.35 x 10(-3) mm2/s. ADC and v(e) were negatively correlated (r = -.60, P < .02). Parameters sensitive to water distribution and geometry (T(1), v(e), tau(i) and ADC) correlated with a multivariable linear regression model. CONCLUSION: The analysis presented here is sensitive to longitudinal changes in breast tumor status; K(trans) and ADC are most sensitive to these changes. Relationships between parameters provide information on water distribution and geometry in the tumor environment.     

基AT89C51多路信号检测和语音报警器的设计

以AT89C51为核心,采用单片语音录放芯片ISD1420和A/D转换器ADC0809,设计了多路信号检测和语音报警器,包括信号放大、处理电路,A/D转换电路,语音报警模块、显示模块、键盘输入模块等.     

基于CMOS工艺的10位逐次逼近型模数转换器设计分析

逐次逼近型模数转换器由于性能折衷而得到了广泛的应用。其中，比较器和数模转换器的精度和速度极大地限制了整个系统的性能。因此，具有失配校准功能的比较器是逐次逼近型模数转换器的关键。设计了10bit逐次逼近型模数转换器中的比较器，对比较器的电路结构和工作原理有较详细的论述。     

基于FPGA的高速并行A/D采样控制电路的设计

给出了一种基于FPGA的高速并行A／D采样控制电路的设计方法．该电路能与各种单片机系统进行友好连接，能够实现高速A／D采集转换和转换后的数据存取．文中以ADC0809为例，详细介绍了含有FIFO存储器的MD采样控制电路的设计方法，并给出了A／D采样控制电路的VHDL源程序和整个采样存储的顶层电路原理图。