基于北斗无源授时的战术电台同步技术研究

同步实现是战术跳频电台最关键的技术。随着北斗卫星导航系统的正式运营，利用北斗无源授时服务提供的时钟作为战术跳频电台的同步参考时钟成为了可能。这种同步技术解决了用户位置容易暴露和用户数量容易饱和的问题，而且可以使初始同步和迟入网同步时间大大降低。对无源授时同步法的性能分析表明，这种同步方案实现简单，同步时间短、同步可靠性高、同步保持时间长，是战术跳频电台中非常具有前景的一种同步方案。     

MPSK信号的载波同步参数最大似然估计的研究

运用最大似然准则分别推导了对于MPSK信号的数据辅助SNR估计方法、判决引导SNR估计方法和一种新的盲信噪比估计方法,对其进行仿真,并与其它一些SNR估计算法进行了比较。通过仿真的结果显示数据辅助的SNR方法性能优越,新的盲SNR估计算法对BPSK信号真有估计范围广、精度高和复杂度小的特点。     

一种新型的OFDM系统频率同步方案

提出了一种正交频分复用(OFDM)系统的频率同步方案。该方案包含一个细同步算法和一个粗同步算法。细同步算法是对MOOSE算法的改进,使其频率捕获范围扩大一倍;粗同步算法通过对特殊的长训练序列进行频域相关运算,来估计大范围的频率偏移,它与改进的细同步算法相结合,能够纠正达到半个系统带宽的频偏。仿真表明这是一种准确而可靠的频率同步方案。     

MSK信号的Turbo同步

Turbo码的提出使系统的性能对同步参数变得极为敏感。文章利用Turbo同步的方法来对Turbo系统进行迭代参数估计,并用插值的方法来减少译码复杂度,最后针对MSK信号给出同步算法。仿真结果表明,在少量增加译码复杂度的情况下,Turbo同步能够使系统获得与严格同步近似的性能。     

短波突发通信快速同步技术研究

对PN序列的捕获问题,介绍了串行捕获和并行捕获两种方案,在此基础上介绍了一种改进的门限自适应的快速同步技术,适用于短波高速数据传输。     

一种OFDM系统的频差补偿同步方法

一般的系统同步要求以定时同步为先，然后进行频偏的估计，但大频差偏移往往影响到了系统的符号粗同步定时。针对大频差下信号难以捕获的问题，文中提出预设频差补偿的同步技术。理论分析和仿真结果表明，所采用的同步方法，可以比较准确地完成系统的符号定时同步。     

Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip

In multiprocessor system-on-chip, tasks and communications should be scheduled carefully since their execution order affects the performance of the entire system. When we implement an MPSoC according to the scheduling result, we may find that the scheduling result is not correct or timing constraints are not met unless it takes into account the delays of MPSoC architecture. The unexpected scheduling results are mainly caused from inaccurate communication delays and or runtime scheduler’s overhead. Due to the big complexity of scheduling problem, most previous work neglects the inter-processor communication, or just assumes a fixed delay proportional to the communication volume, without taking into consideration subtle effects like the communication congestion and synchronization delay, which may change dynamically throughout tasks execution. In this paper, we propose an accurate scheduling model of hardware/software communication architecture to improve timing accuracy by taking into account the effects of dynamic software synchronization and detailed hardware resource constraints such as communication congestion and buffer sharing. We also propose a method for runtime scheduler implementation and consider its performance overhead in scheduling. In particular, we introduce efficient hardware and software scheduler architectures. Furthermore, we address the issue of centralized implementation versus distributed implementation of the schedulers. We investigate the pros and cons of the two different scheduler implementations. Through experiments with significant demonstration examples, we show the effectiveness of the proposed approach.     

A Clock Synchronization Algorithm for Multihop Wireless Ad Hoc Networks

In multihop wireless ad hoc networks, it is important that all mobile hosts are synchronized. Synchronization is necessary for power management and for frequency hopping spread spectrum (FHSS) operations. IEEE 802.11 standards specify a clock synchronization protocol but this protocol suffers from the scalability problem due to its inefficiency contention mechanism. In this paper, we propose an automatic self-time-correcting procedure (ASP) to achieve clock synchronization in a multihop environment. Our ASP has two features. First, a faster host has higher priority to send its timing information out than a slower one. Second, after collecting enough timing information, a slower host can synchronize to the faster one by self-correcting its timer periodically (which makes it becoming a faster host). Simulation results show that our ASP decreases 60% the average maximum clock drift as compared to the IEEE 802.11 and reduces 99% the number of asynchronism in a large-scale multihop wireless ad hoc networks.     

Network Synchronization of an Orthogonal CDMA Satellite Communication System

This paper provides the network synchronization of an orthogonal CDMA geostationary satellite system for fixed service communications. It includes the synchronization procedures, the system architecture and the performance evaluation. The main objective is to provide network wide synchronization of all uplink orthogonal CDMA transmissions. This is achieved in steps; first by providing coarse synchronization using the uplink random access channel and then fine sync using innovative tracking control mechanisms. The uplink access channel receiver utilize a parallel/serial search method for rapid code acquisition, while the code tracking of the uplink orthogonal CDMA traffic channel is based on a delay feedback early-late gate in which the sych control resides in the receiver. The proposed system is designed to minimize the onboard complexity and satisfy the performance requirements. As shown in the performance section, the requirement that all uplink transmissions are synchronized to a reference time within 10% of the chip length can be achieved. In addition, the system analysis determines the design parameters values which optimize performance.     

一种快速同步的时钟数据恢复电路的设计实现

时钟数据恢复(CDR)电路是通信传输设备中的重要部分,对于突发式的接收,基于锁相环的传统的CDR往往不能满足其快速同步的要求.对此,文章采用过采样方式基于FPGA设计实现了一种全数字化的155.52Mb/s下的CDR电路.理论分析、仿真和实验测试结果表明,该CDR电路可以有效地对相位变化实现快速同步,有很大的捕捉范围,且系统较锁相环便于集成.