多极化目标特性测量雷达跟踪接收机的设计与性能分析

基于多极化目标特性测量雷达的设计，结合实际应用，给出了多极化目标特性测量雷达跟踪接收机的设计与工程实现，并对影响跟踪精度的因素进行了分析。     

X441对数放大器的原理及其应用

本文主要介绍X441单片对数放大器的基本原理和应用,并列举了一些具体应用电路。     

一种提高微电路外壳使用可靠性的方法

简要分析了白瓷双列直插外壳的失效模式和失效机理，并进行了模拟实验，通过对实验结果的分析，提出对成品微电路进行二次电镀能够提高其外壳的使用可靠性。     

混合集成电路激光功能调值技术

本文提出了激光功能微调技术在高精度混合集成电路上的应用，讨论了关键技术问题，并以实例具体说明。该技术的应用为研制高精度混合集成电路开辟了新途径。     

STN—LCD的新进展

STN-LCD采用新的取向层,消除了残象;采用新的驱动波形,消除了串扰;采用二(口恶)烷、卤化物、链烯基、醚和二苯乙炔,改进了液晶料材的性能,使STN-LCD获得高的对比度、快的响应速度、低的驱动电压;采用有源矩阵驱动方法,消除了帧响应,使STN-LCD获得高的对比度、高的亮度及视频响应速度;使用温度跟踪电路,自动跟踪STN-LCD的阀值电压,使STN-LCD获得宽的工作温度。     

Partial scan design and test sequence generation based on reduced scan shift method

This paper presents a partial scan algorithm, calledPARES (PartialscanAlgorithm based onREduced Scan shift), for designing partial scan circuits. PARES is based on the reduced scan shift that has been previously proposed for generating short test sequences for full scan circuits. In the reduced scan shift method, one determines proch FFs must be controlled and observed for each test vector. According to the results of similar analysis, PARES selects these FFs that must be controlled or observed for a large number of test vectors, as scanned FFs. Short test sequences are generated by reducing scan shift operations using a static test compaction method. To minimize the loss of fault coverage, the order of test vectors is so determined that the unscanned FFs are in the state required by the next test vector. If there are any faults undetected yet by a test sequence derived from the test vectors, then PARES uses a sequential circuit test generator to detect the faults. Experimental results for ISCAS'89 benchmark circuits are given to demonstrate the effectiveness of PARES.     

用于多种组装技术的厚膜导体复合结构

厚膜导体Ｐｄ－Ａｇ／Ａｕ、Ｐｔ－Ｐｄ－Ａｕ／Ａｕ平面复合结构，Ｐｄ－Ａｇ／Ａｕ立体复合结构可使多种组装技术相互兼容。立体复合结构还可有效地降低导体线电阻，减少线损耗。而且，其超声键合性尤佳     

Memory management optimization problems for integrated circuit simulators

In hardware design, it is necessary to simulate the anticipated behavior of the integrated circuit before it is actually cast in silicon. As simulation procedures are long due to the great number of tests to be performed, optimization of the simulation code is of prime importance. This paper describes two mathematical models for the minimization of the memory access times for a cycle-based simulator.An integrated circuit being viewed as a directed acyclic graph, the problem consists in building a graph order on the vertices, compatible with the relation order induced by the graph, in order to minimize a cost function that represents the memory access time. For both proposed cost functions, we show that the corresponding problems are NP-complete. However, we show that the special cases where the graphs are in-trees or out-trees can be solved in polynomial time.     

MOS功率驱动高速脉冲激光器的研究

运用经典电路理论,对MOS功率管的开关特性、驱动原理进行了分析,导出了应用MOS功率管实现高速大电流开关应遵从的原则和方法,并成功地实现了光脉冲上升时间小于5ns、下降时间小于10ns,驱动电流达10～50AP-P激光器电源的要求.     

基于单片机控制的实验线路故障诊断系统

介绍了基于单片机控制技术的强电实验线路故障自动诊断系统的结构及功能,阐述了系统硬件设计、软件设计的基本原理．