用PC机代替打点计时器计时

在匀变速直线运动的实验中，利用PC机的串行接口来记录运动小车通过测量点的时刻值，以此代替打点计时器计时。     

通用型定时控制器的研究

介绍一种通用型电脑定时控制器，描述了该控制器中ＭＣＳ５１单片机系统的硬件设计及软件结构；对这种控制器的应用与扩展做了全面分析。     

On timing Jitter in wavelength-division multiplexed soliton systems

Collision-induced timing shifts in a wavelength-division multiplexed soliton system are computed when damping, amplification, filtering and positive dispersion management following the loss profile are included. A statistical analysis is presented which takes into account the resulting effect of the large number of collisions occurring in the fiber. Analytic expressions are derived for the root mean square timing jitter and the maximum length of error-free transmission with an arbitrary number of channels. An extensive analysis of system performance corresponding to situations with and without filters and/or dispersion management is carried out.     

一种用于调制识别的盲码元定时估计算法

针对通信信号调制识别中的同步分类问题提出一种盲码元定时估计算法,对于调制方式未知的信号,可以估计未知信号的定时同步,得到最佳采样点信息,实现数字信号的同步分类。仿真结果表明本文的算法对于各种信号具有良好的同步效果。     

Fuzzy logic based intersection delay estimation

A fuzzy logic based delay estimation system is proposed and modelled. Conventional method of delay study involves solving static engineering equations in which only technical factors (traffic demand, roadway geometry, and signal control, etc.) are considered and the affect of nontechnical factors (such as weather or visibility) cannot be analyzed since they do not follow a predefined process. The fuzzy logic based delay estimation combines the complex technical and nontechnical factors and is adaptive to the changing driving environment. The rule base of the delay estimation system is constructed either following a mathematical model or from real-time traffic operational data. Simulation and field test of the fuzzy system have shown that fuzzy logic based modelling is a promising approach to improving intersection delay estimation.     

正交复用QAM系统的定时和载波相位跟踪新算法

在数字信号传输系统中，正交复用ＱＡＭ（ＯＭＱＡＭ）是目前最有效的一种抗信道失真传输技术，但它对系统的定时偏移和载波相位误差非常敏感。本文基于高阶累积量技术，导出了一种新的ＯＭＱＡＭ系统定时和载波相位的跟踪算法。计算机仿真证实了这一理论分析结果，并同原有的Ｈｉｒｏｓａｋｉ算法做了比较     

Real R&;D options with time-to-learn and learning-by-doing

We model R&D efforts to enhance the value of a product or technology before final development. Such efforts may be directed towards improving quality, adding new features, or adopting technological innovations. They are implemented as optional, costly and interacting control actions expected to enhance value but with uncertain outcome. We examine the interesting issues of the optimal timing of R&D, the impact of lags in the realization of the R&D outcome, and the choice between accelerated versus staged (sequential) R&D. These issues are also especially interesting since the history of decisions affects future decisions and the distributions of asset prices and induces path-dependency. We show that the existence of optional R&D efforts enhances the investment option value significantly. The impact of a dividend-like payout rate or of project volatility on optimal R&D decisions may be different with R&D timing flexibility than without. The attractiveness of sequential strategies is enhanced in the presence of learning-by-doing and decreasing marginal reversibility of capital effects.     

用光脉冲注入从锁模激光二极管再生低抖动高Q值光时钟

采用１０ＧＨＺ基准时钟光和１０Ｇｂｉｔ／ｓ的数据脉冲信号光注入到锁模激光二极管，降低了周期抖动，当注入功率为－５ｄＢｍ，在基准时钟光波长等于锁模激光二极管的光波长时，获得的最小抖动为０．２５ｐｓ，采用给锁模激光二极管，在注入功率为＋２７ｄＢｍ时，其Ｑ值达３０００。     

SDH光纤传输系统的信道处理及接收定时特性

本文从ＳＤＨ信号流的帧结构和ＳＤＨ光传输系统采用的简单扰码的线路码型出发，分析了系统对信道的要求，提出了对通道带宽、定时恢复、对信号图案抖动抑制等有关系统设备设计参数的计算方法。     

A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices

This paper extends the timing test model in [5] to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixtures' impacts. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, Parallel/Serial RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a test escape of 300 DPM (Defects Per Million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter. Baosheng Wang received his B.S. degree from Beijing University of Aeronautics and Astronautics (BUAA), Beijing, P.R. China, in 1997 and M.S. degree from Precision Instrument & Mechanical Engineering from the Tsinghua University, Beijing, P. R. China in 2000. In 2005, he received his Ph.D. degree in Electrical Engineering from the University of British Columbia (UBC), Vancouver, BC, Canada. During his Master study, he was doing MEMS, Micro Sensors and Digital Signal processing. From 2000 to 2001, he worked in Beijing Gaohong Telecommunications Company as a hardware engineer in ATM technology. Currently, he is a Design-for-Test (DFT) engineer at ATI Technologies Inc., Markham, Ontario, Canada. He publishes widely at international conferences and journals. His primary research interests are time-driven or timing-oriented testing methodologies for System on-a-Chip (SoC). These fields include test time reduction for SRAMs, accelerated reliability test for non-volatile memories, yield analysis for SoC timing tests, SoC path delay timing characterization and embedded timing measurements. Andy Kuo is currently a Ph.D student of System on a Chip (SoC) Research Lab at the Department of Electrical and Computer Engineering, University of British Columbia. He received his M.A.Sc. and B.A.Sc in electrical and computer engineering from University of British Columbia and University of Toronto in 2004 and 2002 respectively. His research interests include high-speed signal integrity issues, jitter measurement, serial communications. Touraj Farahmand received the B.Sc. degree in Electrical Engineering from Esfahan University of Technology, Esfahan, Iran in 1989 and the M.Sc. in Control Engineering from Sharif university of Technology, Tehran, Iran in 1992. After graduation, he joined the Electrical and Computer Research center of Esfahan University of Technology where he was involved in the DSP algorithm development and design and implementation of the control and automation systems. Since October 2001, he has been working in the area of high-speed signal timing measurement at SoC (System-on-a-Chip) lab of UBC (University of British Columbia) as a research engineer. His research interests are signal processing, jitter measurement, serial communication and control. André Ivanov is Professor in the Department of Electrical and Computer Engineering, at the University of British Columbia. Prior to joining UBC in 1989, he received his B.Eng. (Hon.), M. Eng., and Ph.D. degrees in Electrical Engineering from McGill University. In 1995–96, he spent a sabbatical leave at PMC-Sierra, Vancouver, BC. He has held invited Professor positions at the University of Montpellier II, the University of Bordeaux I, and Edith Cowan University, in Perth, Australia. His primary research interests lie in the area of integrated circuit testing, design for testability and built-in self-test, for digital, analog and mixed-signal circuits, and systems on a chip (SoCs). He has published widely in these areas and holds several patents in IC design and test. Besides testing, Ivanov has interests in the design and design methodologies of large and complex integrated circuits and SoCs. Dr. Ivanov has served and continues to serve on numerous national and international steering, program, and/or organization committees in various capacities. Recently, he was the Program Chair of the 2002 VLSI Test Symposium (VTS'02) and the General Chair for VTS'03 and VTS'04. In 2001, Ivanov co-founded Vector 12, a semiconductor IP company. He has published over 100 papers in conference and journals and holds 4 US patents. Ivanov serves on the Editorial Board of the IEEE Design and Test Magazine, and Kluwer's Journal of Electronic Testing: Theory and Applications. Ivanov is currently the Chair of the IEEE Computer Society's Test Technology Technical Council (TTTC). He is a Golden Core Member of the IEEE Computer Society, a Senior Member of the IEEE, a Fellow of the British Columbia Advanced Systems Institute and a Professional Engineer of British Columbia. Yong Cho received the B.S. degree from Kyung Pook National Unviersity, Korea, in 1981 and the M.S. degree from in electrical and computer engineering from the University of South Carolina, Columbia, S.C., in 1988 and the Ph.D. degree in electrical engineering and applied physics from Case Western Reserve University, Cleveland, OH, in 1992. He is currently a Professor with the Department of Electronics Engineering, Konkuk University, Seoul, Korea. His recent research interests include SoC Design and Verification, H/W and S/W co-design, and embedded programming on SoC. Sassan Tabatabaei received his PHD in Electrical Engineering from the University of British Columbia, Vancouver, Canada in 2000. Since then, he has held several senior technical positions at Vector12 Corp, Guide Technology, and Virage Logic. His professional and research interests include mixed-signal design and test, and signal integrity and jitter test methodologies for high-speed circuits and multi-Gbps serial interfaces. He has published several papers and holds a US patent in the area of timing and jitter measurement. Currently, he holds the position of the director for embedded test at Virage Logic Corporation.