用于千兆以太网基带铜缆接收器均衡的甚高频自适应 连续时间Gm-C 二阶带通滤波器的研究和设计

本文设计了用于千兆以太网基带铜缆接收器均衡的甚高频自适应连续时间Gm-C二阶带通滤波器。基于最陡梯度下降算法，带通滤波器的零点在57－340MHz的频率范围内可以自适应地调节，中心频率为1.278GHz。通过外接电阻伺服环路，滤波器中跨导转换器的跨导值不受工艺偏差和温度变化的影响，采用CSMC－HJ0.6μm CMOS工艺器件模型，用Cadence Spectres仿真器仿真了设计的自适应滤波器电路，仿真结果验证了设计原理和设计的电路。系统的最长学习时间为880个参考时钟周期。     

基于MATLAB语言的自动控制原理多媒体教学研究

结合我校自动化专业教学，从培养高素质，复合型人才的角度，在教学中引入目前世界上流行的MATLAB软件，并把MATLAB语言应用于经典控制系统设计和分析中，在自动控制原理多媒体辅助教学方面做了一些有益尝试和探索，取得了满意的教学效果。     

Some degenerate and quasilinear parabolic systems not in divergence form

This paper deals with positive solutions of degenerate and quasilinear parabolic systems not in divergence form: u_t=u^p(Δu+av), v_t=v^q(Δv+bu), with null Dirichlet boundary conditions and positive initial conditions, where p, q, a and b are all positive constants. The local existence and uniqueness of classical solution are proved. Moreover, it will be proved that all solutions exist globally if and only if ab?λ₁², where λ₁ is the first eigenvalue of −Δ in Ω with homogeneous Dirichlet boundary condition.     

CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing

As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features.This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation.These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.     

大功率晶体管的保护电路

大功率晶体管调速系统中作为开关元件使用时，共优点是开关频率比可控硅的高，但是不注意保护就容易损坏。着重研究过电流故障，并对保护作用的影响进行了分析，进而提出了防止过电流的方法和工作原理。     

基因芯片荧光图象采集与分析

描述了基因芯片荧光图象的光学共聚焦成象,大范围高速扫描与控制,数据采集的原理和方法.并讨论了基因芯片荧光图象的分析算法,即模板定位与阈值分割相结合的半自动算法,并将其计算结果与完全采用人工分割算法的结果进行了比较.     

具连续时滞Liénard方程概周期解的存在唯一性

结合Liapunov泛函，研究了具连续时滞Lienard方程概周期解的存在唯一性和安全一致渐进稳定性。     

VLSI Implementation of Forward Error Control Technique for ATM Networks

In asynchronous transfer mode (ATM) networks, fixed length cells of 53 bytes are transmitted. A cell may be discarded during transmission due to buffer overflow or a detection of errors. Cell discarding seriously degrades transmission quality. The quality degradation can be reduced by employing efficient forward error control (FEC) to recover discarded cells. In this paper, we present the design and implementation of decoding equipment for FEC in ATM networks based on a single parity check (SPC) product code using very‐large‐scale integration (VLSI) technology. FEC allows the destination to reconstruct missing data cells by using redundant parity cells that the source adds to each block of data cells. The functionality of the design has been tested using the Model Sim 5.7cXE Simulation Package. The design has been implemented for a 5 ° 5 matrix of data cells in a Virtex‐E XCV 3200E FG1156 device. The simulation and synthesis results show that the decoding function can be completed in 81 clock cycles with an optimum clock of 56.8 MHz. A test bench was written to study the performance of the decoder, and the results are presented.     

Mathematical Modeling, Control, Computer Simulation and Laboratory Experiments of a Spatial Servopneumatic Parallel Robot

In this paper, the special construction of a parallel robot, called spatial servopneumatic multi-axis test facility, will be discussed. The investigations include the following aspects: (i) the laboratory set-up of the robot, (ii) various results obtained in laboratory experiments, taking into account quite different control algorithms and command-input signals, (iii) a comparison of the laboratory experiments with the computer simulations of Part I of this paper, and ({vi}) a quality check of the results compared with the cost of the different controller realizations. The results of both the computer simulations and the laboratory experiments show: (i) The dynamic behavior of the parallel structure can be tremendously improved by using sophisticated nonlinear control algorithms. (ii) This improvement has to be paid by a drastically increased amount of work for deriving the model equations and control algorithms, and by augmented hardware cost of the sensing elements and controller electronics. (iii) Carefully developed model equations and identified model parameters provide theoretical models of the complex parallel structure that are very close to reality. This enables the design engineer to systematically investigate constructive alternatives of the design parameters, sensor and actuator concepts, and control strategies of the MAP prior to their hardware realization.This work has been supported by the German Science Foundation (DFG) under Contract No. Ha 1666/6-3.     

FJZ-250型高速分幅相机时间测量不确定度分析

FJZ-250型高速转镜分幅相机因转镜速度的不可重复性，光机结构的构造原理和控制系统各路高压触发时间的漂移，导致了时间测量的不确定度。为此，须对相机测量数据进行校正。阐述了校正方法、提供了逐幅校正位置误差的修正系数。若以预置转速对应的名义周期值去处理测量结果，则相机的时间测量合成小确定度将达1％，对名义周期值和名义幅间间隔时间值进行修正后，则可降至0.3％。