基于遗传算法的TBDD排序方法

带时间参数的二叉判决图（ＴＢＤＤ）在电路的时滞故障测试中有着重要的应用价值，但其变量排序是用常规方法无法解决的一个优化问题。本文提出一种基于遗传算法的ＴＢＤＤ排序算法。用快速衡量值和ＴＢＤＤ节点数来计算个体的适应度。针对变量排序的特定问题，提出一种模板保序交叉方法。采用知适应的变异概率计算方法，并提出一个适合于ＴＢＤＤ排序问题的变异算法。实验结果表明较好地解决了ＴＢＤＤ的排序问题。     

大型试件的X射线CT检测方法探讨

当对投影长度大于探测器长度的大型试件做平行光束CT时 ,可以认为投影被截断了。从数学上讲 ,这种情况下的解析法重建如滤波反投影法是不适宜的。然而从工程应用上来说 ,这又不是绝对的。就几种情况讨论了通过补充假数据 ,通过在 0～ 2π范围内对试件成像得到了完整的CT切片 ,获得了切片的精确重建     

An IEEE 1149.1 Compliant Test Control Architecture

This paper deals with a design methodology and associated architecture to support the control of on-chip DFT and BIST hardware. The work is general in that it supports numerous test methods, such as partial and full scan, multiple and reconfigurable scan chains, and both test per clock BIST and scan BIST. The results presented here are compatible with the IEEE 1149.1 boundary scan architecture. The work is based on a hierarchical control methodology that includes systems, PCBs and MCMs. Various options for assigning control functions to be on-chip or off-chip are described. A new, partially distributed test control architecture is introduced that includes an internal test bus and distributed local controllers. There are three main modes of control of test resources, namely local static control, dynamic control and global static control. We show how the control mechanism can be implemented together with the IEEE 1149.1 test protocol. The synthesis of the on-chip test control hardware has been automated in a system called CONSYST.     

Behavioral Testability Insertion for Datapath/Controller Circuits

A method for test synthesis in the behavioral domain is described.The approach is based on the notion of adding a test behavior to the normal-mode design behavior. This testbehavior describes the behavior of the design in test mode. Thenormal-mode design behavior and test-mode test behavior are combinedand then synthesized by any general-purpose synthesis system toproduce a testable design with inserted BIST structures. The testbehavior is derived from the design behavior using testabilityanalysis based on metrics that quantify the testability of signalsand variables embedded within behaviors. The insertion method iscombined with a behavioral test scheme thatintegrates a) the design controller and test controller, b) testingof the entire datapath and controller. Examples show that when thetestability insertion procedure is used to modify a behavior beforesynthesis, the resulting synthesized physical implementation isindeed more easily tested than an implementation synthesized directlyfrom the original behavior.     

基于虚拟仪器技术的激光接收器测试系统

本测试系统通过先进的虚拟仪器技术和LabVIEW7．0编程，实现了对传统光学测试仪器的控制并利用信号源和NIPCI-6104E多功能采集卡进行激光接收器模拟仿真；该系统能实时地采集和分析相关测试数据，并能显示、保存和打印最终测试结果。由于使用选进的LabVIEW，编程开发软件和虚拟仪器技术，该系统成为能自动化检测激光接收器各项参数的综合测试系统。实际的测试结果证明，这种方法实用、方便，测量精度高。     

A Graph-Based Approach to Power-Constrained SOC Test Scheduling

The test scheduling problem is one of the major issues in the test integration of system-on-chip (SOC), and a test schedule is usually influenced by the test access mechanism (TAM). In this paper we propose a graph-based approach to power-constrained test scheduling, with TAM assignment and test conflicts also considered. By mapping a test schedule to a subgraph of the test compatibility graph, an interval graph recognition method can be used to determine the order of the core tests. We then present a heuristic algorithm that can effectively assign TAM wires to the cores, given the test order. With the help of the tabu search method and the test compatibility graph, the proposed algorithm allows rapid exploration of the solution space. Experimental results for the ITC02 benchmarks show that short test length is achieved within reasonable computation time.     

Oscillation Test Strategy: A Case Study

In this paper is proposed as a case study the test of a folded cascode operational amplifier using the Oscillation Test Strategy (OTS). This Operational Amplifier (OPA) is chosen in order to evaluate the ability of OTS to test a more complex amplifier than those previously reported. To obtain comparative results, three different types of single-OPA oscillators are employed.A catastrophic-fault injection procedure is carried out using SPICE. In all oscillators, simulation results show that the fault coverage obtained is lower than those previously obtained by many researchers for simpler amplifiers. This fact suggests that OTS might be inconvenient for applications using the OPA targeted in this work and requiring high fault coverage.     

薄栅氧化层斜坡电压TDDB寿命评价

随着超大规模集成电路的不断发展，薄栅氧化层的质量对器件和电路可靠性的作用越来越重要。经时绝缘击穿（TDDB）是评价薄栅氧化层质量的重要方法。文章着重于薄栅氧化层TD-DB可靠性评价的斜坡电压试验方法的研究，基于斜坡电压实验，提取模型参数，分别利用线性场模型和定量物理模型，外推出工作电压下栅氧化层的寿命。通过分析斜坡电压实验时氧化层的击穿过程，提出斜坡电压实验时利用统一模型外推栅氧化层的寿命比较合适。