半导体激光器光束准直系统的功率耦合效率

在长距离无线光通信中，接收点光功率密度与光束发散角平方呈反比关系，为了获得小的发散角和大的功率耦合效率，要求准直系统有较大的数值孔径(NA)，但数值孔径过大会增加像差，因此合理设计功率耦合效率与准直系统的数值孔径就非常重要。该文对半导体激光器光束准直系统中功率耦合效率进行了研究，给出了半导体激光器光束功率耦合效率与k(孔径半径与孔径处等效光束半径之比)的关系表达式，并结合激光器光束准直系统，给出了半导体激光器光束功率耦合效率与准直系统数值孔径的关系表达式。该研究结论对于半导体激光器光束准直系统设计具有参考作用。     

Effect of the Parameters of Three-Mirror Resonators on the Spectral Characteristics of Single-Pulse Laser Generation with Self-Injection of Priming Radiation

Based on a semiclassical theory, investigations were made of the dynamics and spectral composition of pulsed generation with self-injection of priming radiation from the active part of a three-mirror linear resonator, the passive part of which contains an active loss modulator and serves as the output reflector of the laser. It is shown that there exists a range of resonator parameters at which pulsed lasing has virtually a single frequency irrespective of the detuning of the frequencies of the priming radiation and of the nearest eigenmode of the composite resonator. Considering graphically the phase conditions of generation, it is established that among pulsed lasers with self-injection of priming radiation which are constructed on the basis of three-mirror linear and branched resonators, the most efficient for creating single-frequency generation are those in which the length of the main resonator, where generation of the pulse occurs, is larger than the length of the additional one intended for forming the priming radiation. With an inverse ratio of the lengths of the resonators, the conditions of single-frequency pulsed generation becomes dependent on the priming radiation frequency.     

铁路电力试验车软件的设计与实现

介绍了铁路电力试验车软件的设计思想、框架结构及其总体控制策略 ,并就其中的测试程序、数据库管理系统、串口通讯程序、复杂式样报表生成和系统安装程序的设计策略作了叙述。     

Model validation and model structure determination

This paper gives a tutorial overview of basic approaches for model validation and model structure determination.Work partially supported by the Swedish Research Council for Engineering Sciences under contract 98-654.     

托卡马克工程试验混合堆等离子体性能的等值线图分析

本文简要叙述托卡马克工程试验混合堆等离子体概念设计的物理基础,对等离子体性能进行了等值线图(Plasma Operation Contour)分析。根据工程试验混合堆的要求,得出一组等离子体参数。     

A Novel Biomass Supported Na2CO3 System for Flue Gas Desulfurization

The breakthrough and stoichiometric SO2 adsorption efficiencies of a biomass supported Na2CO3 system (80 wt %Na2CO3/straw) have reached 48.9% and 80.6% respectively at a desulfurization temperature of 80℃.     

Er3+掺杂的Bi2O3-B2O3-SiO2玻璃的光谱性质

测试了Bi₂O₃-B₂O₃-SiO₂玻璃中的Er³⁺离子的吸收光谱、发射光谱、⁴I_13/2的荧光寿命、拉曼光谱,及OH^-的傅里叶红外吸收光谱。应用Judd-Ofelt理论计算了该玻璃中的Er³⁺离子的J-O参数、振子强度、⁴I_13/2能级的寿命,从而利用测得的⁴I_13/2的荧光寿命得出了⁴I_13/2能级的量子效率(15%)。由于较低量子效率可能与OH^-有关,所以计算了玻璃中的OH^-浓度,发现其浓度较高(1.66×10¹⁹cm^-1,相当于Er³⁺浓度的3倍)。应用McCumber理论和四能级模型计算了Er³⁺离子的受激发射截面和荧光发射光谱的半峰全宽,结果与通过吸收光谱计算所得基本吻合。根据透射率和折射率的关系计算了折射率,发现和测量值相差很大,说明有较大的散射,通过拉曼光谱和显微镜测试,认为是玻璃中的微小气泡造成的。     

电视机监督检验电磁兼容结果分析和对策

本文讨论了电磁兼容对电视机的技术要求和相应对策。     

Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.     

CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing

As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features.This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation.These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.