Features of a Scan and Clock Resource chip for providing access to board-level test functions

The architecture and some of the specific features of a Scan and Clock Resource (SCR) chip are described. This chip is currently being used in a high-end workstation product to provide access to the testability features of the individual chips and/or printed circuit boards. Using a board-level controller to gain access to the testability features of system components and interfacing the controller to a diagnostics processor (or external tester) is emerging as a common strategy for designing testable digital systems. Based upon experience gained from such an application, controller features that are deemed useful are discussed.This paper is an enhanced version of the author's earlier paper titled Towards a Standard Approach for Controlling Board-Level Test Functions, presented at the IEEE International Test Conference, ITC'90, Washington D.C., September 1990.     

Boundary scan test,test methodology,and fault modeling

The test technique called boundary scan test (BST) offers new opportunities in testing but confronts users with new problems too. The implementation of BST in a chip has become an IEEE standard and users on board level are the next group to begin thinking about using the new possibilities. This article addresses some of the questions about changes in board-level testing and fault diagnosis. The fault model itself is also affected by using BST. Trivial items are extended with more sophisticated details in order to complete the fault model. Finally, BST appears to be a test technique that offers a high degree of detectability on board level, but for diagnosis, some additional effort has to be made.     

Economic modeling of board test strategies

A long and deep recession, coupled with continuous competitive pressure to reduce costs, is forcing many companies to review their test strategies. Testing costs have become a more significant proportion of the overall manufacturing cost even though manufacturing yields have increased dramatically over the past ten or twelve years. This causes attention to be focused on testing costs as a key source of cost reduction. The increased use of DFT and the integration of design and test are very positive moves towards controlling testing costs but other methods employed can often backfire. The increased use of low priced testers is one such method. The pressure to reduce costs, higher process yields and exhortations that testing adds no value can lead the test engineering manager to take the cheap route. In reality this can often turn out to be an expensive decision. The only way to avoid expensive mistakes is to perform an economic analysis of the alternative courses of action. In most cases this is done, but not always in the right manner or with the necessary amount of detail to make the comparisons meaningful. This article discusses the need for effective cost analysis of test strategies and highlights some of the pitfalls.     

Avoiding linear dependencies in LFSR test pattern generators

Linear Feedback Shift Registers (LFSRs) constitute a very efficient mechanism for generating pseudoexhaustive or pseudo-random test sets for the built-in self-testing of digital circuits. However, a well-known problem with the use of LFSRs is the occurrence of linear dependencies in the generated patterns. In this paper, we show for the first time that the amount of linear dependencies can be controlled by selecting appropriate characteristic polynomials and reordering the LFSR cells. We identify two classes of such polynomials which, by appropriate LFSR cell ordering, guarantee that a large ratio of linear dependencies cannot occur. Experimental results show significant enhancements on the fault coverage for pseudo-random testing and support the theoretical relation between minimization of linear dependencies and effective fault coverage.This work was partially supported by NSF grant MIP-9409905, a 1993–94 ACM/IEEE Design Automation Scholarship and a grant from Nissan Corporation. A preliminary version of this work appeared in A Class of Good Characteristic Polynomials for LFSR Test Pattern Generators, in Proc. of IEEE International Conference on Computer Design, Oct. 1994, pp. 292–295, where it received the ICCD'94 Best Paper Award.     

雪崩光电探测器的击穿效应模型分析

基于CMOS工艺制备了空穴触发的Si基雪崩探测器(APD),基于不同工作温度下器件的击穿特性,建立空穴触发的雪崩器件的击穿效应模型。根据雪崩击穿模型和击穿电压测试结果,拟合曲线得到击穿电场与温度的关系参数(dE/dT),器件在250～320 K区间内,击穿电压与温度是正温度系数,器件发生雪崩击穿为主,dV/dT=23.3 mV/K,其值是由倍增区宽度以及载流子碰撞电离系数决定的。在50～140 K工作温度下,击穿电压是负温度系数,器件发生隧道击穿,dV/dT=-58.2 mV/K,其值主要受雪崩区电场的空间延伸和峰值电场两方面因素的影响。     

基于BAS-BP-Bagging模型的光纤陀螺温度补偿

为提高光纤陀螺的输出精度,以天牛须搜索算法(BAS)优化后的BP神经网络模型为基学习器,采用Bagging并行集成学习算法建立了BAS-BP-Bagging温度补偿模型,并对某型号光纤陀螺进行了温度补偿实验。实验结果表明,在-40～+60℃温度变化环境下,该方法补偿后的光纤陀螺温度漂移相较于补偿前减小了近80%,相较于多项式补偿算法减小了55%,相较于BP神经网络补偿算法减小了30%左右。同时该模型在对新鲜样本的补偿过程中表现出了较为优越的泛化性能。     

基于积分宽度法测量发光二极管结温方法的研究

本文提出了一种基于光谱积分宽度法来测量发光二极管(light emitting diode, LED)结温的新方法,并进行了理论分析和实验研究。本方法主要分为光谱数据采集、定标函数的测定和结温测量三个过程。首先,为了测量成本的降低和精度的提高而采用在正常工作电流下采集LED光谱数据,并通过采用不同温度下的光谱积分宽度与选定的某一基准状态下的值逐差可得到线性度达0.99以上的定标函数,并通过此定标函数可实时测定任意状态下的结温。其次,为了比较本方法测量结温的精确性,分别对单色和白光LED采用本方法和业界主流的正向电压法,通过自行设计的基于积分宽度法结温测量系统和美国Mentor Graphics公司的T3Ster型仪器的测量结果进行比较,两种方法测出的结温最大偏差为2.1℃,在可接受的误差范围内。实验结果表明积分宽度法测结温具有高效便捷且低成本的的特点,具有一定的应用前景。     

基于亮度温度模型的多光谱真温反演算法研究

针对传统的非接触式真温反演算法存在反演速度慢和精度低等问题,提出新的基于亮度温度模型的约束真温反演算法(constrained true temperature inversion algorithm,CTTIA)。 在建模过程中,发现发射率和亮度温度存在内在联系:由亮度温度到发射率的普适规律和由发射率到亮度温度的普适规律。通过仿真实验发现当发射率的样本数量巨大时,CTTIA不但可以为实验提供理论指导,还可大大提升发射率样本的选取效率。在1 800 ℃和2 000 ℃两个温度点下建立9个波长通道对被测目标进行测量计算。结果表明,CTTIA与二次测量算法 (second measurement method,SMM) 相比,精度基本相同,反演时间最高节约了82%。说明该方法的研究是非常关键且重要的,是很有研究价值的。     

Polyether-b-Amide Based Solid Electrolytes with Well-Adhered Interface and Fast Kinetics for Ultralow Temperature Solid-State Lithium Metal Batteries

Solid-state lithium metal batteries (SSLMBs) are highly desirable for energy storage because of the urgent need for higher energy density and safer batteries. However, it remains a critical challenge for stable cycling of SSLMBs at low temperature. Here, a highly viscoelastic polyether-b-amide (PEO-b-PA) based composite solid-state electrolyte is proposed through a one-pot melt processing without solvent to address this key process. By adjusting the molar ratio of PEO-b-PA to lithium bis(trifluoromethanesulphonyl)imide (ethylene oxide:Li = 6:1) and adding 20 wt.% succinonitrile, fast Li⁺ transport channel is conducted within the homogeneous polymer electrolyte, which enables its application at ultra-low temperature (−20 to 25 °C). The composite solid-state electrolyte utilizes dynamic hydrogen-bonding domains and ion-conducting domains to achieve a low interfacial charge transfer resistance (<600 Ω) at −20 °C and high ionic conductivity (25 °C, 3.7 × 10⁻⁴ S cm⁻¹). As a result, the LiFePO₄|Li battery based on composite electrolyte exhibits outstanding electrochemical performance with 81.5% capacity retention after 1200 cycles at −20 °C and high discharge specific capacities of 141.1 mAh g⁻¹ with high loading (16.1 mg cm⁻²) at 25 °C. Moreover, the solid-state SNCM811|Li cell achieves excellent safety performance under nail penetration test, showing great promise for practical application.     

成都市PM2.5、PM10变化特征及其与气象因素的关系

为研究气象因素对成都市大气细颗粒物 (PM2.5)、可吸入颗粒物 (PM10) 的影响, 收集了2015―2018 年成都市 PM2.5、PM10的月平均浓度, 采用Pearson 相关分析法, 分析了成都市PM2.5、PM10与气象条件的关系。结果表明： (1) 2015 ―2018 年, 成都市PM2.5、PM10年平均浓度虽然年际间差别较小, 但整体呈现逐年缓慢下降趋势, 2015 年以来成都市的 一系列大气污染控制措施是PM2.5、PM10逐年缓慢下降的原因; 2015―2018 年成都市PM2.5、PM10浓度季节变化特征整体 表现为冬季 > 春季 > 秋季> 夏季。(2) 不同气象因素对成都市PM2.5、PM10月平均浓度的影响程度不同, 降水量与气温 是影响成都市PM2.5、PM10月平均浓度的主要因素, 两者与PM2.5、PM10呈较高的负线性相关, 其中PM2.5、PM10与降水量 的相关系数均为 −0.612, 与月平均气温的相关系数分别为 −0.822、−0.776, 降水会通过捕获大气中的颗粒物来去除 PM2.5、PM10, 而温度的升高会加强PM2.5、PM10等污染物在垂直方向上的对流运动, 从而对成都市污染物浓度的降低起 到重要作用; 日照时数、月平均风速、相对湿度等与PM2.5、PM10月平均浓度整体也呈现负相关, 但与降水量和气温相 比, 日照时数、月平均风速与PM2.5、PM10月平均浓度的相关性较低, 而相对湿度与PM2.5、PM10月平均浓度的相关性则 更加微弱, 表明相对湿度的变化对成都市PM2.5、PM10的积累和扩散影响很小。