Memory Fault Modeling Trends: A Case Study

In recent years, embedded memories are the fastest growing segment of system on chip. They therefore have a major impact on the overall Defect per Million (DPM). Further, the shrinking technologies and processes introduce new defects that cause previously unknown faults; such faults have to be understood and modeled in order to design appropriate test techniques that can reduce the DPM level. This paper discusses a new memory fault class, namely dynamic faults, based on industrial test results; it defines the concept of dynamic faults based on the fault primitive concept. It further shows the importance of dynamic faults for the new memory technologies and introduces a systematic way for modeling them. It concludes that current and future SRAM products need to consider testability for dynamic faults or leave substantial DPM on the table, and sets a direction for further research.     

基于VMD和BP神经网络的轨道病害诊断方法

针对从非线性、非稳态的轨枕振动信号中提取病害特征困难的问题,文中提出一种基于变分模态分解和多尺度排列熵的轨道病害特征提取方法,并采用BP神经网络病害诊断模型进行病害识别.利用变分模态分解方法将采集到的振动加速度信号进行分解,得到若干个本征模态分量.计算这些本征模态分量的多尺度排列熵值,将其作为轨道病害的高维特征向量,以...     

A System-layer Infrastructure for SoC Diagnosis

During IC manufacturing phase, discriminating between good and faulty chips is not enough. In fact, especially in the first phase of the production of a new device, a complete understanding of the possible failures is quickly required to ramp up production yield. For test engineers, dealing with the manufacturing test of Systems-on-chip (SoCs) means to tackle the extraction of diagnostic data from faulty chips. Another equally important aim of diagnosis, in a later step of a product lifecycle, is to find the real root cause of silicon misbehaviors for field returns. At the core test layer, the adoption of diagnosis-oriented Design-for-Testability structures is almost mandatory and many solutions have been worked out for several types of cores; diagnosis data retrieval often consists in the execution of a set of self-test procedures whose application order and/or customization may depend on the obtained results themselves. This paper details the characteristics of a system-layer test architecture able to manage efficiently SoC self-diagnostic procedures. This architecture is composed of a diagnosis-oriented Test Access Mechanism (TAM) and an Infrastructure-IP owning enough intelligence to automatically manage core diagnostic procedures. Both of them have been designed in compliance with the IEEE 1500 Standard for Embedded Core Test and exploit the characteristics of Self-Test structures inserted for the diagnosis of memory, processor and logic cores. This approach to SoC diagnosis minimizes ATE memory requirements for pattern storage and drastically speeds up the complete execution of diagnostic procedures. Experimental results highlight the convenience of the approach with respect to alternative ATE driven diagnosis procedures, while resorting to negligible area overhead.

Hard-Fault Detection and Diagnosis During the Application of Model-Based Data Converter Testing

The concept of model-based test was developed in order to reduce the production test effort for data converters (Cherubal and Chatterjee (IEEE Trans Circuits Syst part I 50(3):317–327, 2003); Stenbakken and Souders (1985) Modelling and test point selection for data converter testing. In: ITC, Int Test Conf, pp 813–817; Wegener and Kennedy (IEEE Trans Circuits Syst I 51(1):213–217, 2004); Wrixon and Kennedy (IEEE Trans Instrum Meas IM-48(5):978–985, 1999)). In applying this concept, a vector of model parameters is determined for each device under test (DUT). Typically, this model parameter vector is merely used to calculate the DUT performance characteristic which is then subject to specification-oriented testing. However, each element of the model parameter vector represents an independent error source which contributes to performance degradations; thus, the model parameter vector can be viewed as a signature of the error sources. In this work, analyzing the error source signature is used to devise a model-based methodology for hard-fault detection and diagnosis. We investigate conditions under which hard-faults are detectable/diagnosable in spite of masking effects due to manufacturing process variations. In particular, we show that taking the model parameter vector as the fault signature is optimal as it minimizes the masking effects and thus maximizes detectability/diagnosibility.

基于参考信号的无源互调故障定位技术

研究了一种基于参考信号的无源互调故障定位技术.该技术比传统无源互调测量技术多了一个参考信道,提供参考信号,解调互调信号相位响应,同时引入校准技术,在测量端口构建参考平面,通过频时转换得到相对于参考平面的时域响应,有效地进行故障排查.在此基础上,仿真故障定位实验验证了理论的正确性,设计并制造相位参考板,测试结果与实际值比较表明：电缆上两个故障位置实际值与测量值之差的绝对值均≤1m,实际相对误差分别约为5.1%、2.4%,证明了这种方法的正确性和可行性.该技术将克服传统故障定位的不足,更适应于恶劣的地域环境.     

雷达对抗侦察接收机故障智能诊断系统神经网络构建与仿真

针对目前电子对抗装备快速故障检测与维护保障的需要,研究了某型雷达对抗侦察接收机故障智能诊断系统神经网络的建模方法,阐述了网络神经元的选取、网络结构的确定以及网络训练步骤等,并进行了网络训练仿真和网络实例测试,验证了系统故障诊断结果的可信性。     

基于改进双端法的高压交流输电线路故障定位

现有输电线路行波故障测距方法由于受行波波速的不确定性以及输电线路弧垂的影响,容易出现较大的定位误差.为此,提出了一种无需波速和线路长度整定的线路故障行波定位方法.利用线路两端的行波信号检测装置记录故障电压行波波头到达时间,同时根据电压行波折反射过程中的传播路径列出关于距离、速度和时间的方程组,经过数学变换可以消去线路弧垂的影响,并在线路上实时在线测量行波速度.用PSCAD软件对双端结构的输电线路进行了仿真,实验结果表明该方法具有好的适应性,在实际测距中对线路电气参数依赖性低,不受故障类型,故障位置和过渡电阻等因素的影响,定位误差较小,原理简单,具有较高的准确性和良好的适用性.     

柴油机OBD系统设计

为了开发低成本的且具有自主知识产权的OBD系统,论文针对高压共轨柴油机电控系统。选取冷却液温度传感器作为典型传感器进行故障诊断分析。设计了故障诊断电路,研究了故障诊断策略。通过MATLBASIMULINK仿真方法对故障诊断策略进行理论研究。最后在发动机试验台上进行故障诊断试验。该设计能够准确可靠的确诊故障并给出合适的处理结果。为整个OBDII系统设计提供经验。     

电力多媒体视频会议系统故障诊断知识库建立的研究

本文从运维实际工作出发,针对现场视频会议维护经验,探索建立电力多媒体视频会议系统故障诊断知识库,对故障诊断知识库构建、知识库动态数据更新进行了详细阐述,以期提升维护人员维护效率,提高电力行业中视频会议系统的运营管控能力,使电力系统不断的发展。     

MATLAB在电力系统三相短路故障分析中的应用

该文借助MATLAB功能搭建了电力系统模型并仿真了其三相短路故障,通过该软件对故障发生后所得数据波形的分析,从而说明了MATLAB在电力系统研究方面是一个有力的辅助工具,掌握其使用方法对电力系统研究具有重要的实际意义。