A realistic defect oriented testability methodology for analog circuits

Owing to the non-binary nature of their operation, analog circuits are influenced by process defects in a different manner compared to digital circuits. This calls for a careful investigation into the occurrence of defects in analog circuits, their modeling related aspects and their detection strategies. In this article, we demonstrate with the help of a real CMOS circuit that simple test stimuli, like DC, transient and AC, can detect most of the modeled process defects. Silicon devices tested with the proposed test methodology demonstrate the effectiveness of the method. Subsequently, the proposed test method is implemented in production test environment along with the conventional test for a comparative study. This test methodology is structured and simpler, therefore results in substantial test cost reduction.     

Algorithms for I DDQ measurement based diagnosis of bridging faults

In the absence of information about the layout one is left with no alternative but to consider all bridging faults. An algorithm for diagnosis of a subset of such faults, viz. single two line bridging faults in static CMOS combinational circuits is presented. This algorithm uses results from I _DDQ measurement based testing.Unlike known diagnosis algorithms, this algorithm does not use fault dictionaries, it uses only logic simulation and uses no fault simulation. It also uses SOPS, a novel representation of subsets of two-line bridging faults resulting in an efficient algorithm.In spite of the large number of faults that we consider, our experimental results point to the computational feasibility of I _DDQ Measurement based diagnosis of single two line bridging faults. It also shows the effectiveness of reducing the set of possible faults using I _DDQ measurements.A preliminary version of this work was presented at the 29th ACM/IEEE Design Automation Conference, 1992.Research Partially Supported by NSF Grant No. MIP-9102509.This work was performed when the author was with the Dept. of Computer Science, State University of New York at Buffalo.     

电子线路可靠性容差分析与故障诊断方法的研究现状

容差分析是可靠性设计的基础，故障诊断是维持产品可靠性的基本方法。容差分析与故障诊断是提高电工产品的设计质量并保证其工作稳定性和可靠性的重要手段。由综合分析了电子线路可靠性容差分析与故障诊断方法的研究现状，以指出了该领域的发展方向。     

PLS: A versatile tool for industrial process improvement and optimization

Modern industrial processes are characterized by acquiring massive amounts of highly collinear data. In this context, partial least‐squares (PLS) regression, if wisely used, can become a strategic tool for process improvement and optimization. In this paper we illustrate the versatility of this technique through several real case studies that basically differ in the structure of the X matrix (process variables) and Y matrix (response parameters). By using the PLS approach, the results show that it is possible to build predictive models (soft sensors) for monitoring the performance of a wastewater treatment plant, to help in the diagnosis of a complex batch polymerization process, to develop an automatic classifier based on image data, or to assist in the empirical model building of a continuous polymerization process. Copyright © 2008 John Wiley & Sons, Ltd.     

Multiple fault detection in two-level multi-output circuits

It is often stated that in irredundant two-level logic circuits, a test set for all single stuck faults will also detect all multiple stuck faults. We show by a simple example that this result does not hold for multi-output circuits even when each output function is prime and irredundant. Using a result from the programmable logic array technology, we give an output ordering constraint that, if satisfied during test generation, will make a single stuck fault test set a valid multiple stuck fault test set for irredundant two-level multi-output circuits.     

I DDQ testing in CMOS digital ASICs

I _DDQ testing with precision measurement unit (PMU) was used to eliminate early life failures caused by CMOS digital ASICs in our products. Failure analysis of the rejected parts found that bridging faults caused by particles were not detected in incoming tests created by automatic test generation (ATG) for stuck-at-faults (SAF). The nominal 99.6% SAF test coverage required to release a design for production was not enough! This article shows how I _DDQ testing and supplier process improvements affected our early life failure rates over a three year period. A typical I _DDQ measurement distribution, effects of multiple I _DDQ testing, and examples of the defects found are presented. The effects of less than 99.6% fault coverage after the I _DDQ testing was implemented are reviewed. The methods used to establish I _DDQ test limits and implement the I _DDQ test with existing ATG testing are included. This article is a revision of one given at International Test Conference [1].     

红外热成象技术对印刷电路板故障的诊断能力

随着半导体工业的迅速发展，印刷电路板（ＰＣＢ）故障的检测和诊断已经成国ＰＣＢ制造过程中的一个核心问题。本文介绍了红外热成象技术（ＩＩＴ）检测ＰＣＢ故障的原理。详细分析了ＩＩＴ对各种ＰＣＢ故障的检测和诊断能力，并与传统的自动测试设备（ＡＴＥ）作了比较。由于ＩＩＴ检测的非接触性和直观性，ＩＩＴ可望成为ＰＣＢ制造中一 有效的质量保证手段。     

快速制取人体组织病理切片的超声波法

本文介绍了用超声波方法快速制妈人体组织病理切片的基本原理，实验步骤和试验结果。结果表明，用超声波处理后快速制取的病理切片完全怀可常规石蜡切片相媲美，在临床外检快速病理诊断应用上，超声处理仪有可能取代价格昂贵的恒温式冷冻切片机。     

Effect of off-orientation of seed crystal on silicon carbide (SiC) single-crystal growth on the (11 $$\bar 2$$ 0) surface0) surface

The effect of off-orientation growth has been investigated in terms of stacking fault formation during physical vapor transport (PVT) growth of silicon carbide (SiC) single crystals on the (11 0) seed crystal surface. Occurrence of stacking fault formation is largely dependent on the direction of off-orientation, and basal plane stacking fault density is significantly reduced by growing the crystals on a (11 0) seed crystal off-oriented toward 〈0001〉. The density of the basal plane stacking faults rapidly decreases from 100–150 cm⁻¹ to ∼10 cm⁻¹ as the degree of off-orientation is increased from 0 to 10 deg. The results are interpreted in the framework of microscopic facet formation during PVT growth, and the introduction of off-orientation of seed crystal is assumed to prevent (01 0) and (10 0) microfacet formation on the (11 0) growing surface through modification of the surface growth kinetics and to suppress the stacking fault formation. An erratum to this article is available at .     

基于小波包变换的模拟电路故障诊断

把小波包变换用于模拟电路故障诊断中。由于输出信号的各频率成分能量的变化表征了电路中某些元器件的损坏情况,因此,利用小波包变换有效地提取故障特征信息,提出了“能量——故障”的故障诊断方法。计算和实验结果表明：该方法可以快速高效地进行模拟电路故障诊断与定位。